MT90500AL Mitel, MT90500AL Datasheet
MT90500AL
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MT90500AL Summary of contents
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... From Secondary External UTOPIA ATM SAR Interface Multi-Channel ATM AAL1 SAR DS5171 MT90500AL streams at 2.048, 4.096, or 8.192 Mbps for up to 2048 TDM 64 kbps channels • Compatible with ST-BUS, MVIP, H-MVIP and SCSA interfaces • Supports master and slave TDM bus clock operation • ...
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MT90500 Applications • B-ISDN (Broadband ISDN) systems requiring flexible N x 64kbps transport • Connecting TDM backplane to TDM backplane over ATM network (GO-MVIP MC4, or other) • Systems requiring ANSI T1.630 Structured Data Transfer services for 1 to 122 ...
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Introduction ...
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MT90500 4.3.2 TX_SAR Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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System Level Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MT90500 Figure 1 - MT90500 Block Diagram...................................................................................................................12 Figure 2. Pin Connections ................................................................................................................................26 Figure 3 - TDM Clock Selection and Generation Logic .....................................................................................29 Figure 4 - TDM Frame Buffer to External Memory Transfer..............................................................................33 Figure 5 - Transmit Circular Buffer Control Structure ...
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Figure 47 - Local TDM Bus Output Parameters - Negative Frame Pulse ........................................................ 121 Figure 48 - Local TDM Bus - Positive Frame Pulse, 2/4 Sampling .................................................................. 122 Figure 49 - Local TDM Bus - Negative Frame Pulse, 3/4 Sampling................................................................. ...
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MT90500 Table 1 - Primary UTOPIA Bus Pins ................................................................................................................19 Table 2 - Secondary UTOPIA Bus Pins ...........................................................................................................20 Table 3 - Microprocessor Bus Interface Pins ...................................................................................................20 Table 4 - External Memory Interface Pins ........................................................................................................21 Table 5 - Master Clock, Test, and ...
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Table 49 - TDM I/O Register ........................................................................................................................... 100 Table 50 - TDM Bus Type Register................................................................................................................. 101 Table 51 - Local Bus Type Register ................................................................................................................ 102 Table 52 - TDM Bus to Local Bus Transfer Register....................................................................................... 102 Table 53 - Local ...
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MT90500 Table 99 - MT90500 Connections to 32/36-bit Synchronous SRAM................................................................138 Table 100 - MT90500 UTOPIA Signal Directions...............................................................................................140 Table 101 - Recommended TDM Channel Numbers for SRTS VCs .................................................................145 Table 102 - Limits on CDV on Receive SRTS VC..............................................................................................146 Table 103 ...
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... TDM bus links operating at 2.048, 4.096 or 8.192 Mbps (compatible with MVIP / H- MVIP, SCSA and Mitel ST-BUS). On the ATM interface side, the MT90500 provides the UTOPIA bus standardized by the ATM Forum. The device provides the AAL1 Structured Data Transfer (referred to as SDT from now on in this document) and pointerless Structured Data Transfer mappings defi ...
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MT90500 MT90500 To/From Main TX UTOPIA External UTOPIA MUX PHY Interface RX UTOPIA BLOCK From Secondary UTOPIA Module External UTOPIA SAR Interface 1.2 Reference Documents MT90500 Programmer’s Manual. MSAN-171 - TDM Clock Recovery from CBR-over-ATM Links Using the MT90500. ITU-T ...
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ATM Glossary AAL - ATM Adaptation Layer ; standardized protocols used to translate higher layer services from multiple applications into the size and format of an ATM cell. AAL0 - native ATM cell transmission; proprietary protocol featuring 5-byte header ...
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... VTOA - Voice and Telephony over ATM; intended to provide voice connectivity to the desktop, and to provide interoperability with existing N-ISDN and PBX services. Glossary References: The ATM Glossary - ATM Year 97 - Version 2.1, March 1997 The ATM Forum Glossary - May 1997 ATM and Networking Glossary (http://www.techguide.com/comm/index.html) Mitel Semiconductor Glossary of Telecommunications Terms - May 1995. 14 ...
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Features 2.1 General The MT90500 device external interfaces are: • TDM (Time Division Multiplexed) bus composed of 16 serial streams running 8.192 Mbps, plus related clocks and control signals, configurable by software. This interface also includes ...
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MT90500 • Supports partially-filled cells (AAL1, CBR-AAL5, and CBR-AAL0). • User-defined, per-VC, Cell Delay Variation tolerance 128 ms buffer size ( CDV). • Handles TDM channels at 64 kbps granularity. • Each individual VC can ...
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IEEE 1149 (JTAG) Boundary-Scan Test Access Port for testing board-level interconnect. • Packaging: 240-pin PQFP. 2.8 Interrupts The MT90500 provides a wide variety of interrupt source bits, allowing for easy monitoring of MT90500 operation. All interrupt source bits, including ...
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MT90500 • TDM Read Underrun Error Interrupt • TDM Read Underrun Counter Rollover Interrupt 2.8.6 Timing Module Interrupts • 8 kHz Reference Failure Interrupt • SRTS TX Underrun Interrupt • SRTS TX Overrun Interrupt • SRTS RX Underrun Interrupt • ...
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Pin Descriptions I/O types are: Output (O), Input (I), Bidirectional (I/O), Power (PWR), or Ground (GND). Input pad types are: TTL, CMOS, Differential, or Schmitt. The notations “PU” and “PD” are used, respectively, to indicate that a pad has ...
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MT90500 Pin # Pin Name I/O 70, 71, 72, 73, STXDATA[7:0] I 74, 75, 76 STXSOC I 68 STXEN I 67 STXCLAV O 85 STXCLK I Note: MT90500 Secondary UTOPIA port emulates a PHY device for connection to ...
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Table 4 - External Memory Interface Pins Pin # Pin Name I/O 98 MEMCLK O 147 MEM_CS0L O 176 MEM_CS0H O 148 MEM_CS1L O 177 MEM_CS1H O 178, 179, 149, MEM_WR[3:0] O 150 180 MEM_OE O 123, 122, 121, MEM_ADD[17:0] ...
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MT90500 Table 5 - Master Clock, Test, and Power Pins Pin # Pin Name I/O 87 MCLK I 78 RESET I 97 TMS I 93 TCK I 95 TDI I 96 TDO O 94 TRST 16, 29, ...
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Pin # Pin Name I/O 25, 23, 22, 19, ST[15:0] I/O 18, 17, 15, 14, 12, 11, 10 230 CLKx2PI I 227 CLKx2NI I 233 CLKx1 I/O 232 FSYNC I CORSIGA ...
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MT90500 Table 7 - Reset State of I/O and Output Pins Pin Name I/O Reset State PTXDATA[7:0] O Active during and after reset. PTXPAR O Active during and after reset. PTXCLK I/O High-impedance PTXEN O Active during and after reset. ...
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Table 7 - Reset State of I/O and Output Pins Pin Name I/O Reset State LSYNC O Active during and after reset. LOCSTo O Active during and after reset. CLKx2/CLKx2PO I/O Input CLKx2NO O High-impedance Note: All pins are placed ...
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MT90500 IO_VDD_3V IO_VSS IO_VDD_5V IO_VSS RING_VDD_3V RING_VSS IO_VDD_5V IO_VSS RING_VDD_3V RING_VSS PLLCLK IO_VDD_5V REF8KCLK CLKx2NI CLKx2NO IO_VSS CLKx2PI CLKx2/CLKx2PO FSYNC CORSIGB WR/R\W RDY/DTACK IO_VDD_5V 26 180 178 176 174 172 170 168 166 182 AEM 184 A15 A14 186 A13 ...
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PIN PQFP 128 126 124 122 IO_VDD_3V 120 IO_VSS 118 MEM_ADD14 MEM_ADD13 MEM_ADD12 ...
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MT90500 4. Functional Description As shown in Figure 1, “MT90500 Block Diagram,” on page 12, the MT90500 device consists of the following major components: TDM Module, External Memory Controller, TX_SAR, RX_SAR, UTOPIA Module, Clock Recovery, Microprocessor Interface, and Test Interface. ...
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CLKx2 CLKx1 FSYNC FS_INT Master/Slave FSYNC MCLK SEC8KEN FS_INT 1 SEC8K EX_8KA_INT 0 SEC8KSEL 0 1 Square ATM Cells SEC8K_SQ SRTS Clock MT90500 FNXI External CPU Bus Figure 3 - TDM Clock Selection and Generation Logic • The CLKx2 signal ...
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... The REF8KCLK output pin of the MT90500 is intended to provide a clock reference to an optional external PLL. This signal would usually kHz frame pulse, but other signals are possible. The external PLL (e.g. Mitel MT9041) can be used to multiply the REF8KCLK output to 16.384 MHz (or 32.768 MHz) and attenuate jitter. ...
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... REF8KCLK selection multiplexer. The EX_8KA_SQ bit controls the squaring function for the EX_8KA signal. See the register 6090h. Mitel PLLs will typically work with either a pulse 8 kHz square 8 kHz, but other PLL implementations may require a square 8 kHz reference input ...
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MT90500 4.1.2 TDM Interface Operation 4.1.2.1 Main TDM Bus Operation The main TDM bus (pins ST[15:0]) supports SCSA, MVIP, H-MVIP, ST-BUS, and IDL protocols. These buses have different frame sync pulse orientations and different data sampling specifications, as well as ...
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Local Bus Data Transfer Process A local bus data transfer process is provided, which allows local serial TDM input (LOCSTi) data to be output on the main TDM bus (ST[15:0]) in place of the usual data from the internal ...
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MT90500 4.1.3.2 Transmit Circular Buffer Control Structures To minimize the amount of external memory required for the TDM Data to External Memory Process, only the TDM channels assigned to be transmitted over the ATM link are transferred to external memory. ...
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Transmit Circular Buffers The location of the Transmit Circular Buffers in external memory is determined by TXCBBASE (TX Circular Buffer Base Address), found in register 6044h. The first Transmit Circular Buffer is located at TXCBBASE. The second is located ...
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MT90500 4.1.4.2 External Memory to Internal Memory Control Structures To know which internal frame buffer TDM channels need to be written (generally, only the TDM channels scheduled for transmission on the TDM bus), the MT90500 uses control data from the ...
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Internal Memory B “0_0000_0000” <8:0> <20:9> EMIM 4 15 EIMCSBASE EIMCSL 6042h Structure of the Receive Circular Buffer Address and Size Fields Figure 7 - External Memory to Internal Memory Control Structure External ...
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MT90500 4.2 External Memory Controller The external memory controller block of the MT90500 resides between the internal blocks and the external memory. It receives memory access requests from the internal blocks (TDM Interface, TX_SAR, RX_SAR, UTOPIA, and Microprocessor modules) and ...
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Addressing Mode Byte Address MEM_ADD[14: 128K Bank 1 32K*4bytes 128K - 256K Bank 2 32K*4bytes 256K - 384K 384K - 512K 512K - 640K 640K - 768K 768K - 896K 896K - 1024K 1024K - 1152K 1152K ...
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MT90500 MEMCLK MEM_CSnx MEM_WR READ Address1 READ Address2 ADDRESS READ 1 DATA MEMCLK MEM_CSnx MEM_WR READ Address1 READ Address2 ADDRESS READ 1 DATA MEMCLK MEM_CSnx MEM_WR READ Address1 READ Address2 ADDRESS DATA MEMCLK MEM_CSnx MEM_WR READ Address1 ADDRESS DATA It ...
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MEMCLK MEM_CS0x MEM_CS1x Bank 0 ADDRESS Bank 0 DATA MEMCLK MEM_CS0x MEM_CS1x Bank 0 ADDRESS Bank 0 DATA MEMCLK MEM_CS0x MEM_CS1x Bank 0 ADDRESS DATA Figure 11 - Read / Read Turnaround Cycles All of the above features are programmable ...
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MT90500 4.3 TX_SAR Module 4.3.1 TX_SAR Overview 4.3.1.1 General The TX_SAR block is responsible for performing CBR (Constant Bit Rate) cell assembly functions from the TDM port towards the ATM Primary UTOPIA interface, which is typically connected to a PHY ...
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The cell parameters are configured through the microprocessor port. Figure 12 gives examples of the ATM AAL1 cell formats. The MT90500 meets the ...
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MT90500 8 Figure 14 - CBR-AAL5 Cell Format 44 CBR-AAL5 Cell GFC / VPI VPI VPI VCI VCI - The least-significant bit of the VCI PTI CLP PTI field must be set HIGH ...
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Transmit Event Scheduler Overview 4.3.1.3.1 Introduction The distinctive characteristic of AAL1, and the other Constant Bit Rate techniques supported by the MT90500, is that they carry isochronous data, i.e. data that arrives at the SAR at a constant rate. ...
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MT90500 can be set to a length of 47 (long end = 46, long/short = 0), and programmed with one cell event have described. A typical application of the MT90500 might have the first of the three schedulers ...
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Using for an example the case of N=6, we would program the AAL1 scheduler with 6 cell events over 46/47 frames: (7 turns * 47 frames/turn * 6 bytes/frame turn * 46 frames/turn * 6 bytes/frame) = 375 ...
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MT90500 4.3.2 TX_SAR Process Figure 19 at the end of this section gives an overview of the processes explained below. A theoretical overview of scheduler operation is given above, in Section 4.3.1.3. 4.3.2.1 Transmit Event Schedulers As discussed in Section ...
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TESBAA 2010h TESBAB 2020h TESBAC 2030h <20:0> Pointer to Start of Event Scheduler Minimum Scheduler Length - 1 frame Maximum Scheduler Length - 256 frames Pointer Short End Pointer Long End Pointer to Start of Event Scheduler 20 SBASE (from ...
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MT90500 4.3.2.2 Transmit Control Structures Within each frame within a transmit event scheduler 8, 16 Pointers can be programmed. Each entry represents a request to the hardware to generate a cell on that VC. An entry can ...
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First Entry A +02 HEC AS Current Entry SEQ + Offset +06 GFC / +08 VPI(7:0) VPI(11:8) +0A VCI(11:0) TX Circular Buffer Address +0C V (bits<20:6>) TX Circular Buffer Address +0E V (bits<20:6>) TX ...
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MT90500 partially-filled cells, much lower values should be written in this field, thus reducing transmission delay. The following equations (used to calculate the initial “Circ. Buf. Pnt.” written by the software) are valid for most cell types: AAL1 ...
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First Entry HEC 20182 Current Entry 20184 Offset 20186 GFC / 20188 VPI(11:8) VCI(11:0) 2018A TX Circular Buffer Address 2018C V TX Circular Buffer Address 2018E V TX Circular Buffer Address 20190 V Figure Sample ...
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MT90500 Transmit Event Scheduler - one for each type of AAL data (3 schedulers possible) Controls scheduling of transmission of VCs within frames • • • Transmit Control Structures - one for each Main ...
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Non-CBR Data Cell Transmission Capability The TX_SAR also has the ability to transmit CPU-written non-CBR data cells directly from a user-defined FIFO in external memory (the Transmit Data Cell FIFO) to the UTOPIA module. Non-CBR data cells include OAM ...
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MT90500 +00 +02 +04 +06 +08 +0A +0C +0E +10 +32 +34 +36 +38 +3A +3C +3E Figure 21 - Transmit Non-CBR Data Cell Structure Format GFC or VPI(7:0) VCI(15:12) VPI(11:8) VCI(11:0) PTI, etc. HEC ...
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The RX_SAR Module Figure 30 at the end of this section gives an overview of the processes explained below. 4.4.1 RX_SAR Overview The RX_SAR block performs cell identification and reassembly functions on data moving from the Primary UTOPIA Port ...
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MT90500 4.4.2.1 RX_SAR Control Structures The RX_SAR Control Structure is quite similar to the Transmit Control Structure shown in Figure 16, but it has added cell delay variation control fields (as seen in Figure 22). The “First Entry”, “Current Entry”, ...
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Three cell delay variation control fields must be initialized by the software: the “Minimum Lead”, “Maximum Lead” and “Average Lead”. Each of these fields is concatenated with “00” (i.e. multiplied have a range from 0 to 1020. ...
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MT90500 4.4.2.3 Receive Overruns and Underruns The “First Entry” and “Last Entry” fields in the RX_SAR Control Structure point to the first and last RX Circular Buffer Base Address pointers in the RX_SAR Control Structure. The “Minimum Lead”, “Maximum Lead”, ...
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Registers 3022h and 3032h are used to maintain statistics on the occurrence of RX_SAR underrun and overrun conditions. The last VC where an underrun or overrun condition was detected is also recorded in the event ID registers 3020h and 3030h. ...
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MT90500 4.5 UTOPIA Module On the ATM transmit side, the MT90500 multiplexes ATM cells generated by the internal TX_SAR module with ATM cells coming from the Secondary UTOPIA Port. Cells coming from the Secondary UTOPIA Port may be generated by ...
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SECONDARY UTOPIA PORT DEVICE BOUNDARY PRIMARY UTOPIA PORT Figure 25 - Mux and Internal FIFO Sub-Module Block Diagram 4.5.2 Cell Transmission and Mux Process The general block diagram of the Mux and internal FIFO sub-module is shown above. The ...
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MT90500 c) The cell’s VPI field (8 bits) is examined. A bit by bit comparison of the VPI is performed using the contents of both the VPI Match Register (4012h) and the VPI Mask Register (4014h bit value ...
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YES ‘1’ ‘0’ OAMSEL Cell Discarded YES OAM Data Cell placed in RX Data Cell FIFO Use RX_SAR Control Structure Address in Look-up Table Figure 26 - Receive Cell Selection Process PHY (checks HEC) UTOPIA Interface Primary RX Port Incoming ...
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MT90500 LUTBASE + “00000” VPI VCI 00 (M bits) (N bits) (LUTBASE + “00000”) + VPVCC RXBASE RX Structure Address (from 4000 Circular Buffer Base Address 12 RX_SAR Write Pointer Circular Buffer ...
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Non-CBR Data Cell Reception Ability As mentioned above, the MT90500 is capable of receiving non-CBR data cells as well as CBR cells. Non-CBR cells can be received on the UTOPIA bus and written into the user-defined Receive Data Cell ...
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MT90500 Figure 29 - Received Non-CBR Data Cell Internal Format Should the CPU not read the appropriate data cells or should a huge concentration of non-CBR cells arrive consecutively on the Primary UTOPIA Port, a Receive Data Cell FIFO Overrun ...
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VC Look-up Table Determines which VCs are controlled by which RX_SAR Control Structures • • • RX_SAR Control Structures - one for each VC UTOPIA Module RX UTOPIA BLOCK, Main From including External UTOPIA OAM and PHY Interface VPI/VCI Filtering ...
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MT90500 4.6 Clock Recovery from ATM Link 4.6.1 Adaptive Clock Recovery Sub-Module Adaptive Clock Recovery is a flexible method for TDM clock recovery from an ATM link. There are several approaches to adaptive clock recovery, and the standards do not ...
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Bad SNP BAD_SNP next sequence (good SNP) - When going to In_Sync or Bad SNP state, generate one timing reference pulse for each timing cell received. (“Bad SNP” is bad Sequence Number Protection, meaning a bad CRC, ...
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... Clock Recovery from CBR-over-ATM Links Using the MT90500” for applications of Synchronous Residual Time Stamp clocking. Please note that Mitel has entered into an agreement with Bellcore with respect to Bellcore’s U.S. Patent No. 5,260,978 and Mitel’s manufacture and sale of products containing the SRTS function. However the purchase of this product does not grant the purchaser any rights under U ...
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SRTS Transmit Divider Register f Gapping Control B CLKx1 Byte Counter f Generator service byte clock B S ATM Physical Layer Divide by x Network Clock A 4-bit RTS value is generated once ...
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MT90500 Receive ATM Cells its w/ CSI b SRTS Receive Divider Register f Gapping Control B CLKx1 f Generator service byte clock B S ATM Physical Layer Network Clock 4.6.2.2 Receive SRTS Operation ...
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UTOPIA interface MT90500 DEVICE TDM Port (MVIP, ST-BUS, SCSA) CLKx1 FSYNC CORSIGD SRTSDATA EXTERNAL LOCAL REFERENCE TIMING GENERATION CIRCUIT (Small FPGA) Note 1: In ATM receive applications, SRTSDATA corresponds to the 4-bit SRTS calculated as the difference between the locally-generated ...
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MT90500 UTOPIA interface MT90500 DEVICE TDM Port (MVIP, ST-BUS, SCSA) CLKx1 FSYNC CORSIGD SRTSDATA External Data Latch/Buffer (Small FPGA) Note 1: In ATM receive applications, SRTSDATA corresponds to the 4-bit difference calculated between the locally-generated RTS code and the remotely-generated ...
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Microprocessor Interface 4.7.1 General This interface allows an external control device (microprocessor) to configure and confirm the status of the MT90500 via access to internal control and status registers and access to the external device memories. It supports a ...
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MT90500 4.7.3 Microprocessor Access and Device Reset Upon hardware reset (using the RESET pin) of the MT90500, the microprocessor registers go to their respective reset states, as indicated in the register descriptions. Further, the SRES bit in Register 0000h is ...
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... Boundary Scan Instructions The TAP Controller of the MT90500 supports the following instructions: IDCODE, SAMPLE, BYPASS, EXTEST, HIGHZ, CLAMP, and INTEST. 4.8.4 BSDL A BSDL (Boundary Scan Description Language) file is available from Mitel Semiconductor to aid in the use of the IEEE 1149 test interface. TCLK TDI TDO ...
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MT90500 5. Register Map 5.1 Register Overview 5.1.1 General This section describes the registers contained within the MT90500. The MT90500 is mapped over 128 Kbytes of address space, which is divided into two halves by the state of the AEM ...
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Interrupt Structure The MT90500 uses a two-level interrupt structure, as shown in Figure 38. For each of five major modules (TX_SAR, RX_SAR, UTOPIA, TDM Interface and TDM Clock) there is a Status register containing one or more status bits, ...
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MT90500 5.1.3 Register Summary Address Reset Label Hex Value Microprocessor Interface Registers 0000 MCR 0000 0002 MSR 00X0 0010 Reserved 0000 0012 Reserved 0001 0030 WTEMC 0000 0032 Reserved 0000 0034 Reserved 0000 0036 RDPAR 0000 0040 MEMCNF 0008 TX_SAR ...
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Address Reset Label Hex Value 401C VCITIM 0000 401E LUTBA 0000 4020 RXDFBA 0000 4022 RXDFWP 0000 4024 RXDFRP 0000 TDM Interface and Clock Interface Registers 6000 TDMCNT 0000 6002 TIS XX00 6004 CORSIG 0000 6010 TDMTYP 0000 6020 LBTYP ...
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MT90500 5.2 Register Description 5.2.1 Microprocessor Interface Registers Address: 0000 (Hex) Label: MCR Reset Value: 0000 (Hex) Label Bit Position Type TDM_INTE 0 R/W TX_SAR_INTE 1 R/W RX_SAR_INTE 2 R/W MUX_INTE 3 R/W TIM_INTE 4 R/W Reserved 10:5 R/W PAGE_MODE ...
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Address: 0002 (Hex) Label: MSR Reset Value: 00X0 (Hex) Label Bit Position Type TIM_SERV 4 R/O Reserved 6:5 R/0 SERVICE 7 R/O Reserved 15:8 R/O Table 14 - Window to External Memory Register - CPU Address: 0030 (Hex) Label: WTEMC ...
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MT90500 Table 16 - Memory Configuration Register Address: 0040 (Hex) Label: MEMCNF Reset Value: 0008 (Hex) Bit Label Type Position ADDMODE 1:0 R/W CPBANK 2 R/W READLEN 5:3 R/W RWTA 6 R/W RRTA 7 R/W 8 R/W 9 R/W 10 ...
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TX_SAR Registers Address: 2000 (Hex) Label: TXSC Reset Value: 0000 (Hex) Label Bit Position Type SAENA 0 R/W SBENA 1 R/W SCENA 2 R/W TXFFENA 3 R/W AUTODATA 4 R/W TXFFORIE 5 R/W SCHEDULE_IE 6 R/W TXFFRP+ 7 R/W ...
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MT90500 Address: 2002 (Hex) Label: TXSS Reset Value: 0000 (Hex) Bit Label Type Position SCHEDULE 6 R/O/L Reserved 14:7 R/O TXSERV 15 R/W Table 19 - TX_SAR Scheduler Base Register Address: Scheduler A: 2010 (Hex); Scheduler B: 2020 (Hex); Scheduler ...
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Address: Scheduler A: 2014 (Hex); Scheduler B: 2024 (Hex); Scheduler C: 2034 (Hex) Label: TESERA; TESERB; TESERC Reset Value: 0000 (Hex) Label Bit Position Type SINGLE 3 R/W Reserved 5:4 R/W AAL5_INIT 7:6 W/O Reserved 15:8 R/O Table 22 - ...
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MT90500 Table 25 - Transmit Data Cell FIFO Read Pointer Register Address: 2054 (Hex) Label: TXDFRP Reset Value: 0000 (Hex) Label Bit Position Type TXFFRP 6:0 R/O Reserved 15:7 R/O 90 Description Transmit Data Cell FIFO Read Pointer. Indicates the ...
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RX_SAR Registers Address: 3000 (Hex) Label: RXSCR Reset Value: 0000 (Hex) Label Bit Position Type APEMS 0 R/W ACEMS 1 R/W SNEMS 2 R/W PPEMS 3 R/W POREMS 4 R/W APEIE 5 R/W ACEIE 6 R/W SNEIE 7 R/W ...
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MT90500 Address: 3002 (Hex) Label: RXSSR Reset Value: 0000 (Hex) Bit Label Type Position Reserved 4:0 R/O APE 5 R/O/L ACE 6 R/O/L SNE 7 R/O/L PPE 8 R/O/L PORE 9 R/O/L WURE 10 R/O/L WORE 11 R/O/L MCR 12 ...
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Table 30 - RX_SAR Underrun Event ID Register Address: 3020 (Hex) Label: RXUEID Reset Value: 0000 (Hex) Bit Label Type Position WURID 15:0 R/W Table 31 - RX_SAR Underrun Event Counter Register Address: 3022 (Hex) Label: RXUECT Reset Value: 0000 ...
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MT90500 5.2.4 UTOPIA Registers Address: 4000 (Hex) Label: UCR Reset Value: 0000 (Hex) Bit Label Type Position RXENA 0 R/W STXENA 1 R/W RRP 2 R/W RXFFENA 3 R/W RXFFWP+ 4 R/W OAMSEL 5 R/W UKSEL 6 R/W RXBASE 9:7 ...
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Table 36 - VPI / VCI Concatenation Register Address: 4010 (Hex) Label: VPVCC Reset Value: 0000 (Hex) Label Bit Position Type N 4:0 R/W M 7:5 R/W Reserved 8 R/W Reserved 15:9 R/O The VC search mechanism uses a table ...
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MT90500 Address: 4018 (Hex) Label: VCMS Reset Value: 0000 (Hex) Label Bit Position Type VCIMASK 15:0 R/W Address: 401A (Hex) Label: VPITIM Reset Value: 0000 (Hex) Label Bit Position Type TIMING VPI 7:0 R/W Reserved 15:8 R/O Address: 401C (Hex) ...
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Table 44 - Receive Data Cell FIFO Base Address Register Address: 4020 (Hex) Label: RXDFBA Reset Value: 0000 (Hex) Label Bit Position Type RXFFBASE 11:0 R/W RXFFSIZ 13:12 R/W Reserved 15:14 R/W Table 45 - Receive Data Cell FIFO Write ...
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MT90500 5.2.5 TDM Interface and Clock Interface Registers Address: 6000 (Hex) Label: TDMCNT Reset Value: 0000 (Hex) Bit Label Type Position TIENA 0 R/W IEENA 1 R/W GENOE 2 R/W CLK_LOOPBACK 3 R/W CABSIE 4 R/W CFAILIE 5 R/W TOBIE ...
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Table 48 - TDM Interface Status Register Address: 6002 (Hex) Label: TIS Reset Value: XX00 Bit Label Type Position Reserved 3:0 R/O CABS 4 R/O/L CFAIL 5 R/O/L TOB 6 R/O/L TRUE 7 R/O/L TRUCR 8 R/O/L TDMSERV 9 R/O ...
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MT90500 Address: 6004 (Hex) Label: CORSIG Reset Value: 0000 (Hex) Label Bit Position Type CORSIGACNF 1:0 R/W CORSIGBCNF 3:2 R/W CORSIGCCNF 5:4 R/W CORSIGDCNF 7:6 R/W CORSIGECNF 9:8 R/W Reserved 10 R/W CORSIGA 11 R/W CORSIGB 12 R/W CORSIGC 13 ...
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Address: 6010 (Hex) Label: TDMTYP Reset Value: 0000 (Hex) Bit Label Type Position TDMFS 1:0 R/W TDMSMPL 3:2 R/W TDMCLK 5:4 R/W TCLKSYN 6 R/W CLKTYPE 7 R/W CLKMASTER 8 R/W CLKALT 9 R/W Reserved 10 R/W BUSHOLD 11 R/W ...
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MT90500 Address: 6020 (Hex) Label: LBTYP Reset Value: 0000 (Hex) Label Bit Position Type LBUSFS 1:0 R/W LBUSSMPL 3:2 R/W Reserved 5:4 R/W LCLKDIV 7:6 R/W STi2LOCSTo 11:8 R/W LOCSTi2STo 15:12 R/W Table 52 - TDM Bus to Local Bus ...
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Table 53 - Local Bus to TDM Bus Transfer Register Address: 6024 (Hex) Label: LOCTDM Reset Value: 0000 (Hex) Label Bit Position Type LOC2TDMTS 6:0 R/W Reserved 7 R/W LOCSTiNUM 14:8 R/W RENA 15 R/W Table Circular ...
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MT90500 Table Circular Buffer Base Address Register Address: 6044(Hex) Label: TXCBBA Reset Value: 0000 (Hex) Label Bit Position Type Reserved 3:0 R/W TXCBBASE 15:4 R/W Table 57 - TDM Read Underrun Address Register Address: 6046 (Hex) Label: ...
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Table 59 - Clock Module General Control Register Address: 6080 (Hex) Label: CMGCR Reset Value: 0000 (Hex) Bit Label Type Position OUT_SYNC_IE 6 R/W TIM_ENA 7 R/W Reserved 15:8 R/O Table 60 - Clock Module General Status Register Address: 6082 ...
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MT90500 Table 61 - Master Clock Generation Control Register Address: 6090 (Hex) Label: MCGCR Reset Value: 00C0 (Hex) Label Bit Position Type REFSEL 1:0 R/W DIVCLK_SRC 2 R/W EX_8KA_SQ 3 R/W SEC8K_SQ 4 R/W BEPLL 5 R/W DIV1...8 7:6 R/W ...
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Table 61 - Master Clock Generation Control Register Address: 6090 (Hex) Label: MCGCR Reset Value: 00C0 (Hex) Label Bit Position Type FREERUN 12:11 R/W Reserved 15:13 R/W Refer to Figure 3, “TDM Clock Selection and Generation Logic,” on page 29 ...
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MT90500 Address: 60A2 (Hex) Label: EVCR Reset Value: 0000 (Hex) Label Bit Position Type Event_Cnt 15:0 R/O Address: 60A4 (Hex) Label: C1CRL Reset Value: 0000 (Hex) Label Bit Position Type CLKx1_Cnt_L 15:0 R/O Address: 60A6 (Hex) Label: C1CRH Reset Value: ...
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Address: 60A8 (Hex) Label: DIVX Reset Value: 2000 (Hex) Label Bit Position Type DIVX 13:0 R/W Reserved 15:14 R/W Address: 60AA (Hex) Label: DIVXR Reset Value: 0FFF (Hex) Label Bit Position Type DIVXN 11:0 R/W Reserved 15:12 R/W Table 69 ...
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MT90500 Table 70 - SRTS Transmit Byte Counter Register Address: 60B2(Hex) Label: SRTBC Reset Value: 0177 (Hex) Label Bit Position Type Byte Number 8:0 R/W Reserved 15:9 R/O Table 71 - SRTS Receive Gapping Divider Register Address: 60B4(Hex) Label: SRRGD ...
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TDM Time Slot Control Address: 7000 + 2N (Hex) - N=0,1,2,...,127 Label: OEM Reset Value: XXXX (Hex) Label Bit Position Type OE 15:0 R/W Each register represents a particular time slot (e.g. 7000h => time slot 0; 70FEh => ...
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MT90500 6. Electrical Specification 6.1 DC Characteristics Parameter 1 Supply Voltage - 5 Volt Rail 2 Supply Voltage - 3.3 Volt Rail 3 Voltage on any I/O pin (except TRISTATE) 4 Voltage on TRISTATE pin 5 Continuous current at digital ...
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Characteristics 13 Differential Input Low Voltage 14 Input Leakage Current Inputs with pull-down resistors Inputs with pull-up resistors 15 Input Pin Capacitance 16 Output HIGH Voltage 17 Output LOW Voltage 18 High Impedance Leakage 19 Output Pin Capacitance a. Typical ...
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MT90500 6.2 AC Characteristics 6.2.1 Main TDM Bus CLKx2PO CLKx1 FSYNC (neg.) FSYNC (pos.) STi/o Table 77 - Main TDM Bus Output Clock Parameters Characteristic Clock Skew - CLKx2PO falling to CLKx1 change CLKx2PO - Output Clock Period 2.048 Mbps ...
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FSYNC t FPD CLKx2PO t SK CLKx1 STo Bit 1, Last Channel Figure 40 - Main TDM Bus Output Clocking Parameters - Positive Frame Pulse FSYNC t FPD CLKx2PO t SK CLKx1 STo Bit 0, Last Channel Figure 41 - ...
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MT90500 Table 78 - Main TDM Bus Data Output Parameters Characteristic STo Delay - Data to Data Change CLKx1 rising and (STo HIGH or STo LOW) to STo change Fast Bus Slow Bus STo Delay - Data to Data Valid ...
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Table 79 - Main TDM Bus Input Clock Parameters Characteristic Clock Skew - CLKx2 falling to CLKx1 change CLKx2 - Input Clock Period 2.048 Mbps bus (4.096 MHz clock) 4.096 Mbps bus (8.192 MHz clock) 8.192 Mbps bus (16.384 MHz ...
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MT90500 FSYNC CLKx2 CLKx1 Bit 1, Last STi Channel STo Bit 1, Last Channel FSYNC CLKx2 CLKx1 Bit 1, Last STi Channel STo Bit 1, Last Channel 118 t t FIS FIH t SIS t SIH Bit 0, Last Bit ...
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FIS FSYNC CLKx2 CLKx1 Bit 1, Last STi Channel STo Bit 1, Last Channel Bit 0, Last Channel Figure 45 - Main TDM Bus - 4/4 Sampling t FIH t SIS t SIH Bit 6, Bit 0, Last Bit ...
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MT90500 6.2.2 Local TDM Bus Table 81 - Local TDM Bus Clock Parameters Characteristic Clock Skew - LOCx2 falling to LOCx1 change LOCx2 Period LOCx2 Pulse Width (HIGH / LOW) LOCx1 Period LOCx1 Pulse Width (HIGH / LOW) Frame Pulse ...
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LSW LSYNC t t LSS LSH t LSD LOCx2 t LSK LOCx1 t LODD LOCSTo Bit 1, Last Channel Bit 0, Last Channel Figure 46 - Local TDM Bus Output Parameters - Positive Frame Pulse t LSW LSYNC t ...
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MT90500 Table 83 - Local TDM Bus Data Input Parameters Characteristic Sym LOCSTi Setup Time - LOCSTi VALID to LOCx1 falling 2/4 Sampling LOCSTi Hold Time - LOCx1 falling to LOCSTi INVALID 2/4 Sampling LOCSTi Setup Time - LOCSTi VALID ...
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LSYNC LOCx2 LOCx1 Bit 1, Last Bit 0, Last LOCSTi Channel Channel LOCSTo Bit 1, Last Channel Bit 0, Last Channel Figure 49 - Local TDM Bus - Negative Frame Pulse, 3/4 Sampling LSYNC LOCx2 LOCx1 Bit 1, Last Bit ...
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MT90500 6.2.3 CPU Interface - Accessing Registers and External Memory Table 84 - Intel Microprocessor Interface Timing - Read Cycle Parameters Characteristic Address Setup - (AEM and A[15:1] t VALID) to (CS and RD asserted) Address Hold - (CS or ...
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Table 85 - Intel Microprocessor Interface Timing - Write Cycle Parameters Characteristic Address Setup - (AEM and A[15:1] VALID) to (CS and WR asserted) Address Hold - ( de- asserted) to (AEM and A[15:1] INVALID) RDY De-asserted - ...
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MT90500 Table 86 - Motorola Microprocessor Interface Timing - Read Cycle Parameters Characteristic Address Setup - (R/W, AEM and A[15:1] VALID) to (CS and DS asserted) Address Hold - ( de- asserted) to (AEM, A[15:1] and R/W INVALID) ...
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Table 87 - Motorola Microprocessor Interface Timing - Write Cycle Parameters Characteristic Address Setup - (R/W, AEM and A[15:1] VALID) to (CS and DS asserted) Address Hold - ( de-asserted) to (AEM, A[15:1] and R/W INVALID) DTACK High ...
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MT90500 6.2.4 Interface with External Memory Table 88 - MCLK - Master Clock Input Parameters Characteristic MCLK Frequency MCLK Period MCLK Pulse Width (HIGH / LOW) Table 89 - External Memory Interface Timing - Clock Parameters Characteristic MEMCLK Period MEMCLK ...
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MCLK MEMCLK MEM_ADD [17:0] ADDRESS1 VALID t OD MEM_CS0H/L MEM_CS1H MEM_WR[3:0] MEM_DAT[31:0] MEM_PAR[3:0] MEM_OE Figure 55 - External Memory Interface Timing - Read Cycle t MEMP t t MEMH MEML ADDRESS2 VALID ...
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MT90500 MCLK MEMCLK MEM_ADD [17:0] MEM_CS0H/L MEM_CS1H/L MEM_WR[3:0] MEM_DAT[31:0] MEM_PAR[3:0] MEM_OE Figure 56 - External Memory Interface Timing - Write Cycle 130 t MEMP t t MEMH MEML ADDRESS VALID ...
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UTOPIA Interfaces 6.2.5.1 Primary UTOPIA Interface Table 92 - Primary UTOPIA Interface Parameters - Transmit Characteristic PTXCLK Period PTXCLK Pulse Width (HIGH / LOW) Input Setup Time - PTXCLAV VALID to PTXCLK rising Input Hold Time - PTXCLK rising ...
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MT90500 Table 93 - Primary UTOPIA Interface Parameters - Receive Characteristic PRXCLK Period PRXCLK Pulse Width (HIGH / LOW) Input Setup Time - (PRXCLAV, PRXEN, PRXSOC asserted and PRXDATA[7:0] VALID) to PRXCLK rising Input Hold Time - PRXCLK rising to ...
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Secondary UTOPIA Interface Table 94 - Secondary UTOPIA Parameters Timing Characteristic STXCLK Period STXCLK Pulse Width (HIGH / LOW) Input Setup Time - (STXDATA[7:0] VALID; STXSOC and STXEN asserted) to STXCLK rising Input Hold Time - STXCLK rising to ...
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MT90500 6.2.6 SRTS User Interface Characteristic SRTS ENA Delay - LOCx1 falling to CORSIGC asserted SRTS DATA Delay - LOCx1 falling to CORSIGD VALID SRTS ENA Hold Time - LOCx1 falling to CORSIGC de-asserted SRTS DATA Hold Time - LOCx1 ...
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CLKx1 (8 MHz) CLKx1 (4 MHz) CLKx1 (2 MHz) (FSYNC not to scale) FSYNC MCCLK (2 MHz) CLKx2 t MCTDZ MCTX (Data In) MC (Data) MCRX (Data Out) t MCCH t t MCCD MCCD t MCTDL t MCRD Figure 61 ...
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MT90500 6.2.8 Boundary-Scan Test Access Interface Table 97 - Boundary-Scan Test Access Port Timing Parameter TCK period width TCK period width LOW TCK period width HIGH TDI setup time to TCK rising TDI hold time after TCK rising TMS setup ...
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Applications 7.1 Board Level Applications Figure 62 shows a general board level application for the MT90500. This shows a high-level view of the device connection to external memory, a CPU, an ATM Physical Layer device, an ATM AAL5 SAR ...
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MT90500 The MT90500 will work with a variety of standard Synchronous SRAM parts. The burst feature of the Synchronous SRAM is not used by the MT90500, and since the SSRAM is not connected to a cache controller, some of the ...
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Figure 63 - UTOPIA Bus Interconnections for Two MT90500s and an AAL5 SAR Figure 63 shows in greater detail an example of the UTOPIA bus connections when two MT90500 devices and a secondary AAL5 SAR are used. Note that the ...
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MT90500 In order to support the multiple SAR configuration shown in Figure 63, while remaining UTOPIA Level 1 compatible, some UTOPIA pin functions in the MT90500 are expanded. Table 100 gives a comparison of the MT90500 to the UTOPIA Level ...
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System Level Applications Figure 64 depicts an ATM adapter card within a work-group hub, switching non-CBR data and CBR voice traffic with 2 internal switching backplanes (a TDM bus, and a packet bus). The MT90500 device interfaces to the ...
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... Figure 66 - Access Product using Internal High Speed Cell Bus on the Backplane 142 ATM Cells on Primary UTOPIA Port Off-the-shelf AAL3/4, AAL5 SAR Management or User Data ST-BUS I/F MT90500 ST-BUS I/F PCM Clocks Off-the-shelf ATM 25, ATM PHY 51 and Transceiver 155 Mbps Legacy Trunks Mitel T1/E1 Framers at 1 Mbps Mitel T1/E1 Legacy Trunks Framers at 1 Mbps Mitel PLL ...
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... Bus 16 x I/F serial MT90500 MT90500 TDM Chip streams Line Card Asynchronous Cell Bus with no timing transfer Figure 67 - TDM Traffic Transport Over a Cell Bus MVIP/ MITEL SCSA MT90210 UTOPIA MT90500 ATM Bus Conferencing Applications MT90820 DSP SCSI Processor MT90810 DSP PC CHASSIS ...
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MT90500 PC-ATM BUS ATM SWITCH FABRIC ATM SWITCH FABRIC ATM SWITCH FABRIC UTOPIA PC CHASSIS Figure 69 - The GO-MVIP, PC-ATM Bus Standard Architecture 144 ATM VIDEO SWITCH COMPRESSION FABRIC CIRCUIT PHY & UTOPIA ATM 25 or OPTICS ATM Bus ...
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... The ITU-T Recommendation I.363.1 provides some guidance on these issues; see the “Convergence Sublayer” section, especially “Source clock frequency recovery method,” and Appendix II. The reader is also directed to the Mitel Semiconductor Application Note in this topic. 7.3.2 SRTS Clock Recovery Considerations The SRTS (Synchronous Residual Time Stamp) method uses the CSI bit in the AAL1 byte to carry time stamp information over the ATM data link ...
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MT90500 2. Network up-link carries ATM net- work clock in one direction, and SRTS information in the other direction. 8 kHz TDM Reference f nx MCA1 UTOPIA Bus TDM TDM Bus Timing Slave 1. MCA1 compares f to TDM clocks, ...
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External Memory Space and Bandwidth Calculations 7.4.1 External Memory Space Requirements This section provides a list of the control and data structures used by the MT90500 which are located in external memory. An estimation of the structure size is ...
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MT90500 • 16 possible VCs • 128 possible VCs • 1024 possible VCs B. RX_SAR Control Structures Each control structure begins with 12 bytes of control data, and is then followed by 2 bytes of information for each TDM channel. ...
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Memory Structure Summary Table 103 - Summary of External Memory Structures External SIze Memory (in bytes) Structure TX Circular Min: 256 Control structure must start Buffer Control Max: 4096 on 512-byte boundary: Structure Register 6040h: TXCBCSBASE = bits<20:9> of ...
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MT90500 Table 103 - Summary of External Memory Structures External SIze Memory (in bytes) Structure External Min: 512 Control structure must start Memory to Max: 8192 on 512-byte boundary: Internal Memory Control Register 6042h: Structure EIMCSBASE = bits<20:9> of External ...
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External Memory Bandwidth Requirements The following section provides estimated external memory bandwidth requirements to support the functionality of the MT90500, excluding negligible non-CBR traffic (i.e. data cells or OAM cells). The following scenarios are examined: 256, 512, and 1024 ...
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MT90500 ATM Receive Process Bandwidth A. Access to VC Look-up Table. Assuming an overall inbound traffic rate of 25.6 Mbps, the External Memory to Internal TDM Memory Structure encounters a maximum of ~60,000 cells per second (i.e. (3.2 Mbytes/s) / ...
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The above maximum requirement defines the theoretical minimum clock frequency the design must achieve to support 1024 X 64 kbps bidirectional channels with 1024 VCs. Assuming a 29% margin for CPU accesses, AAL0 cell processing, and random lost memory access ...
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MT90500 7.6 Other Applications 7.6.1 Payload Switching Figure 71 indicates how the MT90500 can be used as a payload switch. In such an application, TDM data received in the cell payload of one ATM VC can be transmitted from the ...
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The input channel is now automatically written to the shared buffer, and the output channel is automatically read from the shared buffer, resulting in the input channel being written to the output channel. The throughput delay in this setup is ...
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MT90500 7.6.4 SCSA Message Channel Figure 73 shows how the CORSIG/MC pins are used in an SCSA Message Channel application. Typical Message Bus Controller TXDA RXDA CXDA DCLK 156 MCTX MC MCRX CLKx2 MCCLK MT90500 Figure 73 - SCSA Message ...
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Index Pin 1 44-Pin Dim Min Max A - 0.096 (2.45) A1 0.01 - (0.25) A2 0.077 0.083 (1.95) (2.10) b 0.01 0.018 (0.30) (0.45) D 0.547 BSC (13.90 BSC) D 0.394 BSC 1 ...
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Package Outlines 160-Pin Dim Min 0.125 (3.17) b 0.009 (0.22) D 1.23 BSC (31.2 BSC) D 1.102 BSC 1 (28.00 BSC) E 1.23 BSC (31.2 BSC) E 1.102 BSC 1 (28.00 BSC) e 0.025 BSC (0.65 ...
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... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...