CY7C4225 Cypress Semiconductor Corporation., CY7C4225 Datasheet

CY7C4225

Manufacturer Part Number

CY7C4225

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C4225.pdf (25 pages)

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Features

Functional Description

(FIFO) memories with clocked read and write interfaces. All

are 18 bits wide and are pin/functionally compatible to

IDT722x5. The CY7C42X5 can be cascaded to increase FIFO

depth. Programmable features include Almost Full/Almost

Empty flags. These FIFOs provide solutions for a wide variety

of data buffering needs, including high-speed data acquisition,

multiprocessor interfaces, and communications buffering.

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

Cypress Semiconductor Corporation

• High-speed, low-power, first-in first-out (FIFO)

• 64 x 18 (CY7C4425)

• 256 x 18 (CY7C4205)

• 512 x 18 (CY7C4215)

• 1K x 18 (CY7C4225)

• 2K x 18 (CY7C4235)

• 4K x 18 (CY7C4245)

• High-speed 100-MHz operation (10 ns read/write cycle

• Low power (I

• Fully asynchronous and simultaneous read and write

• Empty, Full, Half Full, and Programmable Almost

• TTL-compatible

• Retransmit function

• Output Enable (OE) pin

• Independent read and write enable pins

• Center power and ground for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Depth Expansion Capability

• Space saving 64-pin 10x10 TQFP, and 14x14 TQFP

• 68-pin PLCC

he CY7C42X5 are high-speed, low-power, first-in first-out

memories

time)

operation

Empty/Almost Full status flags

=45 mA)

64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

•

3901 North First Street

controlled by a free-running clock (WCLK) and a write enable

pin (WEN).

When WEN is asserted, data is written into the FIFO on the

rising edge of the WCLK signal. While WEN is held active, data

is continually written into the FIFO on each cycle. The output

port is controlled in a similar manner by a free-running read

clock (RCLK) and a read enable pin (REN). In addition, the

CY7C42X5 have an output enable pin (OE). The read and

write clocks may be tied together for single-clock operation or

the two clocks may be run independently for asynchronous

read/write applications. Clock frequencies up to 100 MHz are

achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

Depth expansion is possible using the cascade input (WXI,

RXI), cascade output (WXO, RXO), and First Load (FL) pins.

The WXO and RXO pins are connected to the WXI and RXI

pins of the next device, and the WXO and RXO pins of the last

device should be connected to the WXI and RXI pins of the

first device. The FL pin of the first device is tied to V

FL pin of all the remaining devices should be tied to V

The CY7C42X5 provides five status pins. These pins are de-

coded to determine one of five states: Empty, Almost Empty,

Half Full, Almost Full, and Full (see Table 2 ). The Half Full flag

shares the WXO pin. This flag is valid in the standalone and

width-expansion configurations. In the depth expansion, this

pin provides the expansion out (WXO) information that is used

to signal the next FIFO when it will be activated.

The Empty and Full flags are synchronous, i.e., they change

state relative to either the read clock (RCLK) or the write clock

(WCLK). When entering or exiting the Empty states, the flag is

updated exclusively by the RCLK. The flag denoting Full states

is updated exclusively by WCLK. The synchronous flag archi-

tecture guarantees that the flags will remain valid from one

clock cycle to the next. As mentioned previously, the Almost

Empty/Almost Full flags become synchronous if the

using an advanced 0.65

ESD protection is greater than 2001V, and latch-up is prevent-

ed by the use of guard rings.

/SMODE is tied to V

•

San Jose

CY7C4425/4205/4215

CY7C4225/4235/4245

April 1995 - Revised August 18, 1997

•

. All configurations are fabricated

N-Well CMOS technology. Input

CA 95134

•

fax id: 5410

408-943-2600

and the

Related parts for CY7C4225

CY7C4225 Summary of contents

Page 1

... Features • High-speed, low-power, first-in first-out (FIFO) memories • (CY7C4425) • 256 x 18 (CY7C4205) • 512 x 18 (CY7C4215) • (CY7C4225) • (CY7C4235) • (CY7C4245) • High-speed 100-MHz operation (10 ns read/write cycle time) • Low power (I =45 mA) CC • ...

Page 2

... PAF SMODE READ POINTER READ CONTROL 42X5–1 RCLK REN TQFP Top View CY7C4425 43 6 CY7C4205 42 7 CY7C4215 41 8 CY7C4225 40 9 CY7C4235 CY7C4245 GND ...

Page 3

... In standard mode of width expansion tied all devices. SS Not Cascaded - Tied Retransmit function is also available in standalone SS mode by strobing RT. I Cascaded - Connected to WXO of previous device. Not Cascaded - Tied CY7C4425/4205/4215 CY7C4225/4235/4245 7C42X5-25 7C42X5- CY7C4235 CY7C4245 ...

Page 4

... IH V < V < Max., Com’ OUT Ind Max., Com’ OUT Ind 15 4 CY7C4425/4205/4215 CY7C4225/4235/4245 Function . Ambient Temperature + +85 C 7C42X5-15 7C42X5-25 7C42X5-35 Min. Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0.4 2.2 V 2 ...

Page 5

... CY7C4425/4205/4215 CY7C4225/4235/4245 Max. Unit 5 7 ALL INPUT PULSES 90% 90% 10% 10% < 42X5–5 7C42X5-15 7C42X5-25 7C42X5-35 Min. Max. Min. Max. Min. Max. Unit 66 ...

Page 6

... 4 CLK t CLKH CLKL ENS t WFF . PAF(E) , then FF may not change state until the next WCLK edge. SKEW1 6 CY7C4425/4205/4215 CY7C4225/4235/4245 7C42X5-15 7C42X5-25 7C42X5-35 Min. Max. Min. Max. Min. Max. Unit 6 ...

Page 7

... After reset, the outputs will be LOW and three-state CLK t t CLKH CLKL NO OPERATION t REF [14] t SKEW2 RSF t RSF t RSF , then EF may not change state until the next RCLK edge. SKEW2 7 CY7C4425/4205/4215 CY7C4225/4235/4245 t REF VALID DATA t OHZ t RSR [16] OE=1 OE=0 42X5–7 42X5–8 ...

Page 8

... FRL t REF OLZ ENS t t REF REF When t < minimum specification, t CLK SKEW2 SKEW2 8 CY7C4425/4205/4215 CY7C4225/4235/4245 [18 42X5– ENH [17] t FRL t t REF SKEW2 D0 42X5–10 (maximum) = either 2 FRL ...

Page 9

... HALF FULL OR LESS HF RCLK REN DATA WRITE t t ENH t A DATAREAD t CLKL t t ENS ENH ENS 9 CY7C4425/4205/4215 CY7C4225/4235/4245 NO WRITE [13] DATA WRITE SKEW1 t WFF WFF t ENH t ENS t A NEXT DATA READ HALF FULL+1 OR MORE HALF FULL OR LESS t HF 42X5–11 42X5–12 ...

Page 10

... If a read is performed on this rising edge of the read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW. t CLKL t t ENS ENH t PAE t ENS t CLKL t t ENS ENH t t ENS ENH Note 20 [21] t PAEsynch t ENS 10 CY7C4425/4205/4215 CY7C4225/4235/4245 n+1 WORDS n WORDS IN FIFO IN FIFO t PAE 42X5– WORDS Note INFIFO t PAEsynch ENS ENH 42X5–14 ...

Page 11

... CY7C4425, 256 – m words inCY7C4205, 512 – m word in CY7C4215. 1024 – m words in CY7C4225, 2048 – m words in CY7C4235, and 4096 – m words in CY7C4245. 26. 64 – words in CY7C4425, 256 – words in CY7C4205, 512 – words in CY7C4215, 1024 – CY7C4225, 2048 – CY74235, and 4096 – words in CY7C4245. ...

Page 12

... ENS WEN Note: 31. Write to Last Physical Location. t CLKL t ENH t DH PAE OFFSET PAF OFFSET t CLKL t ENH t A UNKNOWN PAE OFFSET t CLKH Note CY7C4425/4205/4215 CY7C4225/4235/4245 PAE OFFSET D – 42X5–17 PAF OFFSET PAE OFFSET 42X5–18 42X5–19 ...

Page 13

... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t CLKH Note XIS t PRT RTR 13 CY7C4425/4205/4215 CY7C4225/4235/4245 XIS t RTR . RTR to update these flags. 42X5–20 42X5–21 42X5–22 42X5–23 ...

Page 14

... FIFO have occurred since the last RS cycle. A HIGH pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and t 14 CY7C4425/4205/4215 CY7C4225/4235/4245 [36] Selection Writing to offset registers: Empty Offset Full Offset ...

Page 15

... Notes: 37 Empty Offset (Default Values: CY7C4425 CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127). 38 Full Offset (Default Values: CY7C4425 CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127). Width Expansion Configuration The CY7C42X5 can be expanded in width to provide word widths greater than 18 in increments of 18 ...

Page 16

... WXO RXO 7C4425 7C4205 7C4215 7C4225 7C4235 V CC 7C4235 FF EF PAE PAF WXI RXI READ CLOCK (RCLK) WXO RXO READ ENABLE (REN) 7C4425 7C4205 OUTPUT ENABLE (OE) 7C4215 7C4225 7C4235 7C4235 FF EF PAE PAF WXI RXI 16 CY7C4425/4205/4215 CY7C4225/4235/4245 DATAOUT (Q) EF PAE 42X5–23 ...

Page 17

... AMBIENT TEMPERATURE OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 120 140 120 100 T = =5. OUTPUT VOLTAGE (V) 17 CY7C4425/4205/4215 CY7C4225/4235/4245 NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.1 V =5. = 1.0 V =3.0V IN 0.9 0.8 0.7 0.6 125 FREQUENCY (MHz) TYPICAL t CHANGE vs. A OUTPUT LOADING ...

Page 18

... Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier A65 64-Lead 14x14 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier 18 CY7C4425/4205/4215 CY7C4225/4235/4245 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial ...

Page 19

... Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier A65 64-Lead 14x14 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier 19 CY7C4425/4205/4215 CY7C4225/4235/4245 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial ...

Page 20

... Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier A65 64-Lead 14x14 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier 20 CY7C4425/4205/4215 CY7C4225/4235/4245 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial ...

Page 21

... CY7C4225-10JC CY7C4225-10AI CY7C4225-10ASI CY7C4225-10JI 15 CY7C4225-15AC CY7C4225-15ASC CY7C4225-15JC CY7C4225-15AI CY7C4225-15ASI CY7C4225-15JI 25 CY7C4225-25AC CY7C4225-25ASC CY7C4225-25JC CY7C4225-25AI CY7C4225-25ASI CY7C4225-25JI 35 CY7C4225-35AC CY7C4225-35ASC CY7C4225-35JC CY7C4225-35AI CY7C4225-35ASI CY7C4225-35JI Package Package Name Type A65 64-Lead 14x14 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier ...

Page 22

... Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier A65 64-Lead 14x14 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier 22 CY7C4425/4205/4215 CY7C4225/4235/4245 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial ...

Page 23

... Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier A65 64-Lead 14x14 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack J81 68-Lead Plastic Leaded Chip Carrier 23 CY7C4425/4205/4215 CY7C4225/4235/4245 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial ...

Page 24

... Package Diagrams 64-Lead Thin Plastic Quad Flat Pack A65 64-Pin Thin Quad Flat Pack A64 24 CY7C4425/4205/4215 CY7C4225/4235/4245 ...

Page 25

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C4425/4205/4215 CY7C4225/4235/4245 ...

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