SC16C2550BIN40 NXP Semiconductors, SC16C2550BIN40 Datasheet
SC16C2550BIN40
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SC16C2550BIN40 Summary of contents
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SC16C2550B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Rev. 04 — 15 February 2007 1. General description The SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial ...
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... Ordering options Topside mark SC16C2550BIA44 2550B 16C2550B SC16C2550BIN40 Rev. 04 — 15 February 2007 SC16C2550B Version SOT187-2 SOT617-1 7 1.4 mm SOT313-2 SOT129-1 © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors 4. Block diagram SC16C2550B DATA BUS IOR IOW CONTROL RESET REGISTER CSA SELECT CSB INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC16C2550B SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs terminal 1 index area RXB 3 4 RXA SC16C2550BIBS TXA 5 TXB 6 7 OP2B 8 CSA Transparent top view SC16C2550BIN40 RXB 9 RXA 10 TXA ...
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... NXP Semiconductors Fig 4. Pin configuration for PLCC44 Fig 5. Pin configuration for LQFP48 SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs RXB RXA 11 SC16C2550BIA44 TXRDYB 12 13 TXA TXB 14 OP2B 15 CSA 16 17 CSB ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin HVQFN32 DIP40 PLCC44 LQFP48 CSA CSB GND 13 20 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin HVQFN32 DIP40 PLCC44 LQFP48 RESET RXRDYA - - 34 RXRDYB - - 23 TXRDYA - - 1 TXRDYB - - XTAL1 XTAL2 CDA - 38 42 CDB - 19 21 CTSA CTSB SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin HVQFN32 DIP40 PLCC44 LQFP48 DSRA - 37 41 DSRB - 22 25 DTRA - 33 37 DTRB - 34 38 RIA - 39 43 RIB - 23 26 RTSA RTSB RXA RXB TXA TXB n. SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... NXP Semiconductors 6. Functional description The SC16C2550B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol) ...
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... NXP Semiconductors Table 4. Chip Select CSA, CSB = 1 CSA = 0 CSB = 0 6.2 Internal registers The SC16C2550B provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control ...
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... NXP Semiconductors 6.3 FIFO operation The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 7:6, but not the transmit trigger level. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU ...
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... NXP Semiconductors 6.5 Programmable baud rate generator The SC16C2550B supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s. ...
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... NXP Semiconductors Table 7. Output baud rate (bit/ 110 150 300 600 1200 2400 3600 4800 7200 9600 19.2 k 38.4 k 57.6 k 115.2 k 6.6 DMA operation The SC16C2550B FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an empty location(s) ...
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... NXP Semiconductors converts the serial data back into parallel data that is then made available at the user data interface D0 through D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational ...
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... NXP Semiconductors 7. Register descriptions Table 8 assigned bit functions are more fully defined in Table 8. SC16C2550B internal registers Register Default [2] General register set RHR THR IER FCR ISR LCR MCR ...
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... NXP Semiconductors prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate. After 7 should be shifted to the center of the start bit. At this time the start bit is sampled and still a logic validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character ...
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... NXP Semiconductors 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU when the receive FIFO has reached the programmed trigger level ...
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... NXP Semiconductors regardless of the programmed level until the FIFO is full. RXRDY on PLCC44 and LQFP48 packages transitions LOW when the FIFO reaches the trigger level and transitions HIGH when the FIFO empties. 7.3.2 FIFO mode Table 10. Bit 7:6 5 SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... NXP Semiconductors Table 10. Bit 1 0 Table 11. FCR[ 7.4 Interrupt Status Register (ISR) The SC16C2550B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... NXP Semiconductors Table 13. Bit 7:6 5:4 3:1 0 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits and the parity are selected by writing the appropriate bits in this register. Table 14. Bit 7 6 5:3 2 1:0 Table 15. ...
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... NXP Semiconductors Table 16. LCR[ Table 17. LCR[ 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 18. Bit 7 SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C2550B and the CPU. Table 19. Bit SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Line Status Register bits description ...
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... NXP Semiconductors Table 19. Bit 0 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem or other peripheral device to which the SC16C2550B is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state ...
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... NXP Semiconductors 7.9 Scratchpad Register (SPR) The SC16C2550B provides a temporary data register to store 8 bits of user information. 7.10 SC16C2550B external reset condition Table 21. Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 22. Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB ...
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... NXP Semiconductors 8. Limiting values Table 23. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V voltage on any other pin n T operating temperature amb T storage temperature stg P /pack total power dissipation per package tot 9. Static characteristics Table 24 ...
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... NXP Semiconductors 10. Dynamic characteristics Table 25. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t clock pulse duration w1 t clock pulse duration w2 f oscillator/clock frequency XTAL t address set-up time 6s t address hold time 6h t IOR delay from chip select 7d t IOR strobe width ...
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... NXP Semiconductors Table 25. Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t delay from start to reset 28d TXRDY t RESET pulse width RESET N baud rate divisor [1] Applies to external clock, crystal oscillator max 24 MHz. 1 ------- [2] Maximum frequency = t 3w [3] RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches. ...
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... NXP Semiconductors CSx IOR Fig 9. General read timing active IOW RTS change of state DTR CD CTS DSR INT IOR RI Fig 10. Modem input/output timing SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs t 6h valid address ...
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... NXP Semiconductors EXTERNAL CLOCK ------- XTAL t w3 Fig 11. External clock timing RX INT IOR Fig 12. Receive timing SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit data bits ( data bits ...
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... NXP Semiconductors RX RXRDY IOR Fig 13. Receive ready timing in non-FIFO mode RX RXRDY IOR Fig 14. Receive ready timing in FIFO mode SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit data bits ( start bit ...
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... NXP Semiconductors TX INT active IOW Fig 15. Transmit timing TX active IOW byte #1 TXRDY Fig 16. Transmit ready timing in non-FIFO mode SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit data bits ( data bits ...
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... NXP Semiconductors TX IOW active byte #16 TXRDY Fig 17. Transmit ready timing in FIFO mode (DMA mode ‘1’) SC16C2550B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs start bit data bits ( data bits 6 data bits ...
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... NXP Semiconductors 11. Package outline PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DIP40: plastic dual in-line package; 40 leads (600 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.7 0.51 4 inches 0.19 0.02 0.16 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering 12.1 Introduction There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 12.2 Through-hole mount packages 12 ...
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... NXP Semiconductors Table 26. Package thickness (mm) < 2.5 2.5 Table 27. Package thickness (mm) < 1.6 1.6 to 2.5 > 2.5 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Fig 22. Temperature profiles for large and small components For further information on temperature profi ...
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... NXP Semiconductors To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ...
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... NXP Semiconductors Table 28. Suitability of IC packages for wave, reflow and dipping soldering methods Mounting Package Surface mount BGA, HTSSON..T LFBGA, SQFP, SSOP..T VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS [7] PLCC LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN ...
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... Document ID Release date SC16C2550B_4 20070215 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 2 • Added SC16C2550B_3 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 UART A-B functions . . . . . . . . . . . . . . . . . . . . . 9 6.2 Internal registers 6.3 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4 Hardware/software and time-out interrupts 6.5 Programmable baud rate generator . . . . . . . . 12 6.6 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 13 6.7 Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 13 7 Register descriptions ...