ISP1362 NXP Semiconductors, ISP1362 Datasheet
ISP1362
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ISP1362 Summary of contents
Page 1
... Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be hardware configured to function as a downstream port, an upstream port or an OTG port whereas port 2 can only be used as a downstream port ...
Page 2
... Toshiba MIPS, ARM7/9, Motorola DragonBall™ and PowerPC™ Reduced Instruction Set Computer (RISC): 16-bit data bus 10 Mbyte/s data transfer rate between the microprocessor and ISP1362 Supports Programmed I/O (PIO) or Direct Memory Access (DMA) Supports ‘suspend’ and remote wake-up Uses 12 MHz crystal or direct clock source with on-chip Phase-Locked Loop (PLL) for low Electro-Magnetic Interference (EMI) Operates at +3 ...
Page 3
... Philips Semiconductors 3. Applications The ISP1362 can be used to implement a dual-role USB device in any application—USB host or USB peripheral—depending on the cable connection. If the dual-role device is connected to a typical USB peripheral, it behaves like a typical USB host. The dual-role device, however, can also be connected any other USB host and behave like a typical USB peripheral ...
Page 4
... Description plastic low profile quad flat package; 64 leads; body 1.4 mm plastic thin fine-pitch ball grid array package; 64 balls; body 0.8 mm SOT543-1 Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Version SOT314-2 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 5
... ADVANCED PHILIPS OVERCURRENT SLAVE HOST CONTROLLER ON-THE-GO CONTROLLER PHILIPS DEVICE CONTROLLER DC BUFFER GOODLINK MEMORY 4, 14, 26 40, 52 D_SUSPEND CP_CAP2 D_WAKEUP OTGMODE ISP1362 56 V DD_5V 35 H_PSW1 36 H_PSW2 PROTECTION 42 H_OC1 41 H_OC2 46 H_DM2 USB 47 TRANSCEIVER H_DP2 49 OTG_DM1 OTG 50 TRANSCEIVER OTG_DP1 ...
Page 6
... D7 DGND D10 12 D11 D12 15 D13 16 Fig 2. Pin configuration LQFP64. 9397 750 12337 Product data ISP1362BD Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller H_DP2 46 H_DM2 45 OTGMODE H_OC1 41 H_OC2 ...
Page 7
... Fig 3. Pin configuration TFBGA64. 9397 750 12337 Product data ISP1362EE F ISP1362EE/ ball A1 index area Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller 004aaa151 © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 8
... I/O bit 8 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output I/O bit 9 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362 ...
Page 9
... I/O bit 15 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output - digital ground I read strobe input ...
Page 10
... LOW — switches ON the PMOS providing V port HIGH — switches OFF the PMOS when not in use, leave this pin open open-drain output Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller through resistor CC through resistor CC for details ...
Page 11
... D signal of the OTG port, the downstream host port 1 or the upstream device port; when not in use, leave this pin open and set bit ConnectPullDown_DS1 of the HcHardwareConfiguration register Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller to the downstream BUS pin ...
Page 12
... HIGH — PIO bus of the DC is selected input I/O bit 0 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output I/O bit 1 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362 ...
Page 13
... A) and cables through some termination resistors. The transceiver is compliant with Universal Serial Bus Specification Rev 2.0. 8.6 Overcurrent protection The ISP1362 has a built-in overcurrent protection circuitry. This feature monitors the current drawn on the downstream V exceeds the current threshold. The built-in overcurrent protection feature can be used when the port acts as a host port ...
Page 14
... PIO and direct memory access (DMA) modes. When CS is LOW (active), the address pin A1 has priority over DREQ and DACK. Therefore, as long as the CS pin is held LOW, the ISP1362 bus interface does not respond to any DACK signals. When CS is HIGH (inactive), the bus interface will respond to DREQn and DACKn ...
Page 15
... The buffer memory of the DC follows a similar architecture. Details on the DC memory area allocation can be found in memory does not support the direct addressing mode. 9.1.1 Memory organization for the HC The HC in the ISP1362 has a total of 4096 bytes of buffer memory. This buffer area is divided into four parts (see Table 4: Buffer memory area ...
Page 16
... ATL buffers are further divided into blocks of equal sizes depending on the value written to the HcATLBlkSize register (ATL) and the HcINTLBlkSize register (INTL). The ISP1362 HC supports blocks in the ATL and INTL buffers. Each of these blocks can be used for one complete Philips Transfer Descriptor (PTD) data. ...
Page 17
... The PTD payload, however, is padded to the next DWord boundary when the HC calculates the location of the next PTD header. The ISP1362 HC checks the payload size from the ‘Total size’ field of the PTD itself and calculates the location of the next PTD header based on this information. ...
Page 18
... Fig 6. A sample snapshot of the ISTL memory management scheme. 9.1.2 Memory organization for the DC The ISP1362 DC has a total of 2462 bytes of built-in buffer memory. This buffer memory is multiconfigurable to support the requirements of different applications. The DC buffer memory is divided into 16 areas to be used by control OUT, control IN and 14 programmable endpoints ...
Page 19
... The ISP1362 provides the PIO mode for external microprocessors to access its internal control registers and buffer memory. It occupies only four I/O ports or four memory locations of a microprocessor. An external microprocessor can read or write to the internal control registers and buffer memory of the ISP1362 through the PIO operating mode. ISP1362. ...
Page 20
... Fig 8. PIO interface between a microprocessor and the ISP1362. 9.3 DMA mode The ISP1362 also provides the DMA mode for external microprocessors to access the internal buffer memory of the ISP1362. The DMA operation enables data to be transferred between the system memory of a microprocessor and the internal buffer memory of the ISP1362. ...
Page 21
... The register structure in the ISP1362 is a command-data register pair structure. A complete register access needs a command phase followed by a data phase. The command (also named as the index of a register) is used to inform the ISP1362 about the register that will be accessed at the data phase. ...
Page 22
... When microprocessor accesses the command port. Read 16-bit Rev. 03 — 06 January 2004 Single-chip USB OTG controller command port data port Commands Command register . . . Control registers 004aaa160 Write16-bit A0/ D[15:0] © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 004aaa045 22 of 150 ...
Page 23
... Command phase Writing to a 16/32-bit register 32-bit access 16-bit access Data phase Command phase Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Second data phase for 32-bit register Second data phase for 32-bit register 004aaa046 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 24
... Data phase } 9.5 PIO access to the buffer memory The buffer memory in the ISP1362 can be addressed using either the direct addressing method or the indirect addressing method. 9.5.1 PIO access to the buffer memory by using direct addressing This method uses the HcDirectAddressLength register to specify two parameters required to randomly access the ISP1362 buffer memory (total of 4096 bytes) ...
Page 25
... After the proper value is written to the HcDirectAddressLength register, data is accessible from the HcDirectAddressData register (called as HcDirAddr_Port in the following sample code). A sample code for writing word_size bytes of data from *w_ptr to the memory locations of the ISP1362 buffer starting from the address start_addr is as follows: void direct_write(unsigned int *w_ptr,unsigned int ...
Page 26
... The ISP1362 uses two DMA channels to individually serve the HC and the DC. The DMA transfer allows the system CPU to work on other tasks while the DMA controller transfers data to or from the ISP1362. The DMA slave controller, in the ISP1362, is compatible with the 8327 type DMA controller. ...
Page 27
... Remark: Configure the HcDMAConfiguration register only after you have configured all the other registers. The ISP1362 will assert DREQ1 once the DMA enable bit in this register is set. 9.6.2 Combining the two DMA channels The ISP1362 allows systems with limited DMA channels to use a single DMA channel (DMA1) for both the HC and the DC. This option can be enabled by writing logic 1 to the OneDMA bit of the HcHardwareConfi ...
Page 28
... HcµPInterrupt register OR level 2 (OPR group) level 1 LE LATCH INT1 HcHardwareConfiguration Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller HcµPInterruptEnable register OR HcHardwareConfiguration register InterruptPinEnable From INT2 004aaa395 OneINT register © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 29
... Set the InterruptPinEnable bit to logic 0. To re-enable the interrupt generation: 1. Set all bits in the Hc PInterruptEnable register according to the HCD 2. Set the InterruptPinEnable bit to logic 1. 9.7.2 Interrupt in the DC The registers that control the interrupt generation in the ISP1362 DC are: • • 9397 750 12337 Product data requirements ...
Page 30
... Edge-triggered interrupt: takes no action because it disables the interrupt when the ISR. The interrupt line of the ISP1362 goes back to the inactive state. When the operating system exits the ISR and re-enables the interrupt processing, it sees no pending interrupt result, the interrupt is missed. ...
Page 31
... V 11 s), the internal drops below PORP (using the internal POR circuit Figure 16 shows the availability 004aaa484 A © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 with CC for more trip trip PORP (1) 004aaa482 31 of 150 ...
Page 32
... Dual-role device When port 1 of the ISP1362 is configured in the OTG mode, it can be used as an OTG dual-role device. A dual-role device is a USB device that can function either as a host peripheral host, the ISP1362 can support all four types of transfers (control, bulk, isochronous and interrupt) at full-speed or low-speed peripheral, the ISP1362 can support two control endpoints and confi ...
Page 33
... CHRG_V BUS for about 30 ms [by using DISCHRG_V BUS OtgControl register], optional. pulsing. The ISP1362 allows you to choose which SRP to support and has a BUS by detecting SRP. In this case, it may choose to disable BUS Steps to enable the SRP detection by V – Set A_SEL_SRP (bit 9) of the OtgControl register to logic 0. ...
Page 34
... The B-device must assert the bus reset (that is, SE0) within the time that the A-device turns on its pull-up. the B-device may turn on its DP pull-up at this time. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller ...
Page 35
... Timers: The HNP state machine uses four timers: a_wait_vrise_tmr, a_wait_bcon_tmr, a_aidl_bdis_tmr and b_ase0_brst, tmr. All timers are started on entry to and reset on exit from their associated states. The ISP1362 provides a programmable timer that can be used as any of these four timers. Rev. 03 — 06 January 2004 ...
Page 36
... Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller b_idle drv_vbus/ chrg_vbus/ id loc_conn/ loc_sof/ a_bus_drop/ & (a_bus_req | a_srp_det) a_wait_vrise drv_vbus loc_conn/ loc_sof a_bus_drop | a_vbus_vld | ...
Page 37
... HNP implementation and OTG state machine The OTG state machine is the software behind all the OTG functionality implemented in the microprocessor system that is connected to the ISP1362. The ISP1362 provides all input status, the output control and timers to fully support the state machine transitions in These registers include: • ...
Page 38
... Philips document ISP136x Embedded Programming Guide. 11.5 Power saving in the idle state and during wake-up The ISP1362 can be put in the power saving mode if the OTG device is not in a session. This significantly reduces the power consumption. In this mode, both the DC and the HC are suspended. The PLL and the oscillator are stopped, and the charge pump is in the suspend state ...
Page 39
... Fig 20. External capacitors connection. 12. USB Host Controller (HC) 12.1 USB states of the HC The USB HC in the ISP1362 has four USB states: USBOperational, USBReset, USBSuspend and USBResume These states define the responsibilities of the HC related to the USB signaling and bus states. These signals are visible to the HC Driver (HCD), the software driver of the HC, by using the control registers of the ISP1362 USB HC ...
Page 40
... HcControl register. The HCD is allowed to perform only the USB state transitions shown in 12.2 USB traffic generation USB traffic can be generated only when the ISP1362 USB HC is under the USBOperational state. Therefore, the HCD must set the ISP1362 USB HC into the USBOperational state. This is done by setting the HCFS field of the HcControl register before generating USB traffi ...
Page 41
... Philips Semiconductors 12.3 USB ports The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be configured as a downstream port (host), an upstream port (device dual-role port (OTG). Port fixed downstream port. The function of port 1 depends on two input pins of the ISP1362, namely ID and OTGMODE ...
Page 42
... ActualBytes[7:0] Active MaxPktSize[7:0] B3[3] TotalBytes[7:0] reserved DirToken[1:0] FunctionAddress[6:0] B7[7:0] Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller PTD data #1 PTD data #2 PTD data # Toggle ActualBytes[9:8] Speed MaxPktSize[9:8] TotalBytes[9:8] © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
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... UnexpectedPID 1000 DataOverrun 1001 DataUnderrun 1010 - 1011 - 1100 BufferOverrun 1101 BufferUnderrun Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller [1] Interrupt ISTL (ISO) reserved Last reserved reserved reserved reserved PollingRate[7:5]; StartingFrame StartingFrame[4:0] General Transfer Descriptor (TD) or isochronous data packet processing completed with no detected errors ...
Page 44
... A Paired PTD is a special feature that provides high performance single endpoint bulk transfer and handles set-up enumeration sequence within 1 ms. A paired PTD consists of two PTDs serving the same endpoint of a device that are set active and Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Section 12.6. ...
Page 45
... This section provides an example on how a USB transfer descriptor ‘Get Descriptor’ (commonly used in device enumeration) is used to illustrate the ISP1362 PTD application. To perform this example, make sure the ISP1362 is in the Operational state, and then connect a USB device (for example, a USB mouse port. ...
Page 46
... Frame Supports multi-buffering by using the ISTL0 or ISTL1 toggling mechanism. The CPU can decide (in ms) how fast it can serve the ISP1362. This gives the CPU the flexibility to decide how much time it takes to read and fill in the ISO data. The ISTL buffer can be updated on-the-fly by using the direct addressing memory architecture. Rev. 03 — ...
Page 47
... V power supply instead of the + Rev. 03 — 06 January 2004 Single-chip USB OTG controller . of 150 m , the overcurrent DSon drain C18 0.1 F P_channel gate MOSFET source FB2 C17 0.1 F © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 . When BUS V DD_5V PSU_5V R31 10 k H_PSWn H_OCn 150 ...
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... F for the host port or 4.7 F for the OTG port supply V BUS Rev. 03 — 06 January 2004 Single-chip USB OTG controller OC DETECTION PSU_5V FB2 V OUT EN C17 0.1 F from an external source. In this BUS that will be sensed by BUS © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 H_OCn H_PSWn 48 of 150 ...
Page 49
... In the suspend state, these pins are HIGH. To wake up the HC, these pins must be pulled LOW. The ISP1362 can be partially suspended (only the HC or only the DC). In the partially suspended state, clock circuit and PLL continue to work. To save power, both the HC and the DC must be set to the suspend mode ...
Page 50
... Philips Semiconductors 13. USB Device Controller (DC) The design of the DC in the ISP1362 is compatible with the Philips ISP1181B USB full-speed interface device IC. The functionality of the DC in the ISP1362 is similar to the ISP1181B in the 16-bit bus mode. In addition, the command and register sets are also the same. ...
Page 51
... ESR. If the buffer is full, it empties the buffer so that data can be received by the SIE at the next OUT token phase. The DMA count is complete DMAEN = 0. The DMA count is complete DMAEN = 0. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 52
... Double PIO mode buffering access no yes no yes supported supported lists the programmable buffer memory sizes. Endpoint enable bit (FIFOEN) Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller DMA mode Endpoint type access [2][3] no control OUT [2][3] no control IN supported programmable © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Endpoint description control IN (64-byte fixed) control OUT (64-byte fixed) double-buffered 1023-byte isochronous endpoint 16-byte interrupt OUT 16-byte interrupt IN double-buffered 64-byte bulk OUT double-buffered 64-byte bulk IN © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 53 of 150 ...
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... Intel 8237 DMA controller and has separate address spaces for memory and I/O. 9397 750 12337 Product data Table Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller 14), whether endpoints are enabled © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 55
... O DC requests a DMA transfer I DMA controller confirms the transfer I DMA controller terminates the transfer I instructs the DC to put data on the bus I instructs the DC to get data from the bus © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 55 of 150 ...
Page 56
... DC that the data on the bus lines has been transferred. longer needed. In the Single cycle mode, this is done after each byte or word; in the Burst mode, following the last transferred byte or word of the DMA cycle. data on the bus. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Figure 26. MEMR ...
Page 57
... DcDMACounter register short packet is received and transferred DMAEN = 0 The DMA transfer stops. No interrupt, however, is generated. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller IN endpoint transfer completes as programmed in the DcDMACounter register counter reaches zero in the middle of the buffer ...
Page 58
... The steps leading the DC to the suspend state are as follows the event of no SOF for 3 ms, the DC in the ISP1362 sets bit SUSPND of the 2. When the firmware detects a suspend condition (through the IESUSP), it must 3. In the interrupt service routine, the firmware must check the current status of the 4. To meet the suspend current requirements for a bus-powered device, the internal 5. When the fi ...
Page 59
... Philips Semiconductors The DC in the ISP1362 will remain in the suspend state for at least 5 ms, before responding to external wake-up events, such as global resume, bus traffic, CS active or LOW pulse on the D_SUSPEND/D_WAKEUP pin. Figure 27 USB BUS INT2 GOSUSP (bit) D_SUSPEND/D_WAKEUP CS Fig 27. Suspend and resume timing. ...
Page 60
... The D_SUSPEND/D_WAKEUP pin goes LOW, and the RESUME bit of the after starting the wake-up sequence, the DC in the ISP1362 resumes its 4. In case of a remote wake-up, the DC in the ISP1362 drives a K-state on the USB 5. The application restores itself and other system components to normal operating 6 ...
Page 61
... Remark: This bit is normally set when the A-device goes into the a_suspend state and is cleared when it comes out of the a_suspend state. The LOC_CONN bit must be set before clearing this bit. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller pulsing BUS © ...
Page 62
... OTG port BUS of the OTG port BUS 11 10 SE0_2MS - - - - 3 2 A_SESS_ B_SESS_ A_VBUS_ VLD END © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 BUS BUS through a BUS 9 8 reserved ID_REG VLD 150 ...
Page 63
... ID pin is LOW (mini-A plug is inserted in the device’s mini-AB receptacle) 1 — ID pin is HIGH (no plug or mini-B plug is inserted in the device’s mini-AB receptacle) Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller BUS © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 64
... Single-chip USB OTG controller OTG_TMR B_SE0_ _TIMEOUT SRP - R/W R A_SESS_ B_SESS_ A_VBUS_ VLD_C END_C VLD_C R/W R/W R/W BUS K) is detected when the bus is in the © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 8 A_SRP_ DET 0 R/W 0 ID_REG_C 0 R/W pulsing or data 64 of 150 ...
Page 65
... ID pin is shorted to ground or pulled HIGH). Write logic 1 to clear this bit. Writing logic 0 has no effect. 0 — no event 1 — ID_REG bit has changed Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 66
... ID_REG_IE Logic 1 enables interrupt upon detection of the ID_REG status change. Rev. 03 — 06 January 2004 Single-chip USB OTG controller OTG_ B_SE0_ TMR_IE SRP_IE - R/W R A_SESS_ B_SESS_ A_VBUS_ VLD_IE END_IE VLD_IE R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 8 A_SRP_ DET_IE 0 R/W 0 ID_REG_ 150 ...
Page 67
... These bits define the initial value used by the OTG timer. The timer VALUE interval is 0.01 ms. Maximum timer allowed is 167.772 s. [23:0] Rev. 03 — 06 January 2004 Single-chip USB OTG controller reserved - - - - - - R/W R/W R R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 150 ...
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... CURRENT_TIME Rev. 03 — 06 January 2004 Single-chip USB OTG controller reserved - - - - - - 0.01 ms. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 150 ...
Page 69
... HC operational registers (32 bits). These operational registers are made compatible to Open Host Controller Interface (OpenHCI) operational registers. This enables the OpenHCI HCD to be ported easily to the ISP1362. Reserved bits may be defined in future releases of this specification. To ensure interoperability, the HCD that does not use a reserved field must not assume that the reserved fi ...
Page 70
... Section 15.9.4 on page 107 32 Section 15.9.5 on page 108 32 Section 15.9.6 on page 108 16 Section 15.9.7 on page 108 16 Section 15.9.8 on page 109 Section 15.9.9 on page 109 Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Functionality HC Miscellaneous registers HC Buffer RAM Control registers ISO Transfer registers Interrupt Transfer registers Aperiodic Transfer registers © ...
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... Rev. 03 — 06 January 2004 Single-chip USB OTG controller Table 35 shows the bit allocation of the register © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 150 ...
Page 72
... USBResume state after detecting the resume signaling from a downstream port. The HC enters USBReset after a software reset and a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. - reserved Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller ...
Page 73
... This register is used by the HC to receive commands issued by the HCD reserved - - - - - - reserved - - - - - - reserved - - - - - - reserved - - - - - - Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller SOC[1: © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Rev. 03 — 06 January 2004 Single-chip USB OTG controller 41) provides the status of the events that cause Section 15.1.5) and the MasterInterruptEnable reserved 0 0 R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 R 150 ...
Page 75
... SchedulingOverrunCount (SOC) of HcCommandStatus to be incremented. A bit is set in the HcInterruptStatus register The corresponding bit in the HcInterruptEnable register is set The MasterInterruptEnable (MIE) bit is set. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Table 43 contains © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 76
... SO 0 — ignore 1 — enable interrupt generation because of Scheduling Overrun Rev. 03 — 06 January 2004 Single-chip USB OTG controller reserved - - - - - - reserved R/W R/W - © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 R 150 ...
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... Resume Detect Rev. 03 — 06 January 2004 Single-chip USB OTG controller Table 45 provides the bit allocation of the reserved - - - - - - reserved R/W R/W - © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 R 150 ...
Page 78
... Rev. 03 — 06 January 2004 Single-chip USB OTG controller …continued Table 47) contains a 14-bit value that 27 26 FSMPS[14: R/W R/W R R/W R/W R FI[13: R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 150 ...
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... R/W R FR[7: R/W R/W Rev. 03 — 06 January 2004 Single-chip USB OTG controller Table 49 reserved - - - - - - FR[13: R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 R R 150 ...
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... FN[15: FN[7: Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 81
... LSThreshold: Contains a value that is compared to the FrameRemaining (FR) field before a low-speed transaction is initiated. The transaction is started only if FrameRemaining (FR) this field. The value is calculated by the HCD, which considers transmission and set-up overhead. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Table ...
Page 82
... HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1:NDP POTPGT[7: R/W R reserved - - - - - - NOCP - - R/W Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Table 55 R/W R/W R OCPM DT NPS R/W R R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 83
... When this bit is cleared, the PowerSwitchingMode (PSM) bit specifies global or per-port switching. 0 — ports are power switched 1 — ports are always powered on when the HC is powered on Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller NDP[1:0] ...
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... Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller …continued PPCM[2: R/W R DR[2: R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
Page 85
... Bit 1 — Device attached to port 1 Bit 0 — reserved reserved - - - - - - Rev. 03 — 06 January 2004 Single-chip USB OTG controller reserved - - - - - - CCIC - - R reserved - - - - - - © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 Table 59 for bit LPSC 0 R 150 ...
Page 86
... PortPowerStatus). In the per-port power mode, it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing logic 0 has no effect. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller OCI ...
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... Product data Table 61 reserved - - - - - - PRSC - - R reserved - - - - - - PRS - - R/W Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller OCIC PSSC PESC R/W R/W R LSDA - - R POCI PSS PES R/W R/W R/W © ...
Page 88
... CurrentConnectStatus (CCS) Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to inform the system that the device is attached. - reserved Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 89
... On write—SetPortPower: The HCD writes logic 1 to set the PortPowerStatus (PPS) bit. Writing logic 0 has no effect. Remark: This bit always reads logic 1 if power switching is not supported. - reserved Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 90
... On write—ClearSuspendStatus: The HCD writes logic 1 to initiate a resume. Writing logic 0 has no effect. A resume is initiated only if PortSuspendStatus (PSS) is set. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 91
... PortEnableStatus (PES) bit. Writing logic 0 has no effect. CurrentConnectStatus (CSC) is not affected by any write. Remark: This bit always reads 1B when the attached device is nonremovable (DeviceRemoveable[NDP]). Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 92
... OTG ATX in the suspend mode. 0 — disconnect built-in pull-down resistors on H_DM2 and H_DP2 1 — connect built-in pull-down resistors on H_DM2 and H_DP2 for the downstream port 2 Remark: Port 2 is always used as a host port. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 Table 63 DACKMode 0 ...
Page 93
... InterruptPinEnable 0 — power-up value 1 — global interrupt pin INT1 is enabled; this bit should be used with the Hc PInterruptEnable register to enable pin INT1 Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 94
... ISTL0 (default ISTL1 INTL ATL Direct Addressing 0 — read from the buffer memory of the HC 1 — write to the buffer memory of the HC © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 DMARead WriteSelect 0 0 R/W R 150 ...
Page 95
... Description 0000H Number of data bytes to be read from or written to the buffer RAM. Table 11 10 OTG_IRQ - - - - 3 2 AllEOT ISTL_1_ ISTL_0_ Interrupt INT 0 0 R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 67. 68 ATL_IRQ 0 0 R/W R SOF_INT INT 0 0 R/W R 150 ...
Page 96
... DMA transfer. This bit is set either when the value of the HcTransferCounter register has reached zero, or the EOT pin of the HC is triggered by an external signal. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2004. All rights reserved 150 ...
Page 97
... Single-chip USB OTG controller …continued Table 70 OTG_IRQ_ Interrupt Enable - - R EOT ISTL_1 ISTL_0 Interrupt Interrupt Interrupt Enable Enable Enable R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 8 ATL_IRQ_ Interrupt Enable 0 R/W 0 SOF Interrupt Enable 0 R 150 ...
Page 98
... HC miscellaneous registers 15.5.1 HcChipID register (R: 27H) This register contains the ID of the ISP1362. The upper byte identifies the product name (here 36H stands for the ISP1362). The lower byte indicates the revision number of the product including engineering samples. description of the register. ...
Page 99
... The ISTL1 buffer has not yet been read by the HC. 1 — The ISTL1 buffer has been read by the HC. 0 — The ISTL0 buffer has not yet been read by the HC. 1 — The ISTL0 buffer has been read by the HC. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 75 ISTL1 ...
Page 100
... The HC processes the ISTL1 buffer. 0 — The HC does not process the ISTL0 buffer. 1 — The HC processes the ISTL0 buffer. Table 77 R/W R R/W R R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 R/W R R/W R R/W R/W 100 of 150 ...
Page 101
... Bit 15.7.2 HcISTL0BufferPort register (R/W: 40H/C0H) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the ISTL0 buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the ISTL0 buffer is not allowed. The bit description of the register is given in ...
Page 102
... Hc PInterrupt register to logic 1 and updates the HcBufferStatus register. 15.7.3 HcISTL1BufferPort register (R/W: 42H/C2H) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the ISTL1 buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the ISTL1 buffer is not allowed. The bit description of the register is given in Code (Hex): 42 — ...
Page 103
... Bit INTLBuffer 15.8.2 HcINTLBufferPort register (R/W: 43H/C3H) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the INTL buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the INTL buffer is not allowed. The bit description of the HcINTLBufferPort register is given in Table Code (Hex): 43 — ...
Page 104
... Hc PInterrupt register to logic 1 and updates the HcBufferStatus register. 15.8.3 HcINTLBlkSize register (R/W: 53H/D3H) The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks so that the HC can skip the current PTD and proceed to process the next PTD easily. The block size of the INTL buffer is required to be specified in this register and must be a multiple of 8 bytes ...
Page 105
... Bits[31:0] 1 — The PTD is the last PTD stored in the buffer. Table 92 shows the bit allocation of the register. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Description 0 — The PTD stored in the INTL buffer has not been successfully processed by the HC. ...
Page 106
... Bit ATLBuffer 15.9.2 HcATLBufferPort register (R/W: 44H/C4H) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the ATL buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the ATL buffer is not allowed. The bit description of the HcATLBufferPort register is given in Table Code (Hex): 44 — ...
Page 107
... HcBufferStatus register. 15.9.3 HcATLBlkSize register (R/W: 54H/D4H) The ISP1362 partitions the ATL buffer into several equal sized blocks so that the HC can skip the current PTD and proceed to process the next PTD easily. The block size of the ATL buffer must be specified in this register and must be a multiple of 8 bytes. ...
Page 108
... The PTD is the last PTD stored in the buffer. Table 101 shows the bit allocation of the register. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Description 0 — The PTD stored in the ATL buffer was not successfully processed by the HC. ...
Page 109
... Single-chip USB OTG controller ActivePTD[4: Table 103 PTDDoneCount[4: R/W R/W Description reserved Number of PTDs processed by the HC. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 shows the bit R/W R/W 109 of 150 ...
Page 110
... Single-chip USB OTG controller Table 105 shows the bit allocation R/W R/W R/W Description reserved Maximum allowable time in ms for the HC to retry a transaction with NAK returned. Table © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 R/W 107. 110 of 150 ...
Page 111
... Endpoint 0 OUT Endpoint 0 IN Endpoint DcEndpointStatus register endpoint 0 OUT DcEndpointStatus register endpoint 0 IN Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller [1] Code (Hex) Transaction [2] 20 write 1 byte [2] 21 write 1 byte ...
Page 112
... DcErrorCode register endpoint all registers with write access DcScratch register DcFrameNumber register DcChipID register DcInterrupt register 1023, the firmware must manage the upper byte. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller [1] Code (Hex) Transaction [ read 1 byte (60) ...
Page 113
... Logic 1 indicates that this endpoint has double buffering. FFOISO Logic 1 indicates an isochronous endpoint. Logic 0 indicates a bulk or interrupt endpoint. FFOSZ[3:0] Selects the buffer memory size according to Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Table 108. A bus reset will Table ...
Page 114
... In the 16-bit bus mode, the upper byte is ignored GOSUSP reserved R/W R/W Rev. 03 — 06 January 2004 Single-chip USB OTG controller 3 2 DEVADR[6: R/W R/W R INTENA DBGMOD reserved [1] [ R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 R SOFTCT [1] [1] 0 R/W 114 of 150 ...
Page 115
... Rev. 03 — 06 January 2004 Single-chip USB OTG controller Table 114. A bus reset will not change any CKDIV[3: R/W R/W R WKUPCS reserved INTLVL R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 Table 114). Bus 8 1 R/W 0 INTPOL 0 R/W 115 of 150 ...
Page 116
... Bus reset value: unchanged. INTPOL Selects the INT2 signal polarity (0 = active LOW active HIGH). Bus reset value: unchanged. Table 116. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller 50 %) during the ‘suspend’ state. Logic The clock frequency range is © ...
Page 117
... Logic 1 enables interrupt upon the EOT detection. IESUSP Logic 1 enables interrupt upon detection of a ‘suspend’ state. IERESM Logic 1 enables interrupt upon detection of a ‘resume’ state. IERST Logic 1 enables interrupt upon detection of a bus reset. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller ...
Page 118
... Rev. 03 — 06 January 2004 Single-chip USB OTG controller 11 10 reserved - - - - 3 2 DMAEN reserved 0 - R/W - R/W 120. Writing to the register sets the number of Section 16.1.6 for more details. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 BURSTL[1:0] [1] [ R/W Table 17. 118 of 150 ...
Page 119
... R/W R DMACR[7: R/W R/W Symbol Description DMACR[15:0] DcDMACounter register 2) bytes can be written or read, N representing the size of the 1) divided by 2. After each read or write action, the buffer pointer is Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller R/W R/W R R/W R/W R/W © ...
Page 120
... D[15:0] 2 … … … Table 124. Reading the DcEndpointStatus register will clear the interrupt bit 16.2.3). Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller 2 bytes (isochronous endpoint: N Table Table 123. Description command code (00H to 1FH) ignored packet length data word 1 (data byte 2, data byte 1) data word 2 (data byte 4, data byte 3) … ...
Page 121
... Set-up packet. SETUPT Logic 1 indicates that the buffer contains a Set-up packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller OVER SETUPT CPUBUF WRITE ...
Page 122
... Logic 1 indicates that the secondary endpoint buffer is full. EPFULL0 Logic 1 indicates that the primary endpoint buffer is full. DATA_PID This bit indicates the data PID of the next packet (0 = DATA0 PID DATA1 PID). Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Section Section ...
Page 123
... Logic 1 indicates that a new event occurred before the previous status was read. DATA01 This bit indicates the PID type of the last successfully received or transmitted packet (0 = DATA0 PID DATA1 PID). Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller …continued Section ...
Page 124
... DATA PID; data was ignored Table 131 UNLOCK[15:8] = AAH Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller …continued Table 130 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 125
... Sending data AA37H unlocks the internal registers and buffer memory for writing, following a ‘resume’ R SFIR[7: R/W R/W Symbol Description - reserved; must be logic 0 SFIR[12:0] Scratch Information register Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller SFIR[12: R/W R/W R ...
Page 126
... Word # Description - ignored - command code (B4H) 0 frame number © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 126 of 150 ...
Page 127
... EP10 EP9 EP8 EP2 EP1 EP0IN EOT SUSPND RESUME © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 EP7 EP0OUT RESET 0 R 127 of 150 ...
Page 128
... USB bus. RESUME Logic 1 indicates that a ‘resume’ state was detected. RESET Logic 1 indicates that a bus reset condition was detected. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 128 of 150 ...
Page 129
... Conditions V < > < Conditions 1.8 V tolerant pins 3.3 V tolerant pins 5 V tolerant pins 5 V tolerant pins non 5 V tolerant pins Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Min Max 0.5 +4.6 0.5 +6.0 - 100 [1] 2000 +2000 60 +150 Min Typ Max 3 ...
Page 130
... Conditions DC suspended HC suspended HC and DC are suspended = unless otherwise specified. amb Conditions pin to GND Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Min Typ Max - [ Min Typ Max - - 0 ...
Page 131
... LOAD V ; see Figure 29 BUS(OTG) external capacitor external capacitor external capacitor not driven BUS(OTG) Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Min Typ Max 0 0 0.8 2 0.3 2 ...
Page 132
... Rev. 03 — 06 January 2004 Single-chip USB OTG controller Min Typ - - - - - - - - 4 150 0 200 200 = 281 - 656 - 350 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 Max Unit 300 0 100 132 of 150 ...
Page 133
... Fig 29. Output voltage versus load current. 9397 750 12337 Product data Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller LOAD (mA LOAD (mA) © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 134
... pF; L 90 unless otherwise specified. amb LOAD Conditions = 4 mA; LOAD LOAD Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Min Typ Max [ [ 100 - 500 45 ...
Page 135
... If you are accessing only the DC, then the DC programmed I/O timing applies. If you are accessing both the HC and the DC, then the DC programmed I/O timing applies. Conditions register access buffer access Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Min Typ Max 100 - 200 ...
Page 136
... RLRH t RHRL t RLDV data data valid valid t WHWL WDH data data valid valid Conditions Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller t SLRL t SLWL t RHSH t WHSH RHDZ data data valid valid WDSU data data valid valid ...
Page 137
... Fig 32. DC Programmed interface write timing (I/O and 8237 compatible DMA). 9397 750 12337 Product data t RHAX t AVRL t SHDZ (1) t RLRH t SHRL t RHSH t WHAX t AVWL t WLWH (1) t SHWL t WHSH t WHDZ Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller 004aaa105 004aaa106 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 137 of 150 ...
Page 138
... WSU t WHD Rev. 03 — 06 January 2004 Single-chip USB OTG controller Min Typ Max [ 146 - - t SHAH t AHRH 004aaa107 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 Unit 138 of 150 ...
Page 139
... Fig 34. HC burst mode DMA timing. 9397 750 12337 Product data Conditions 4-cycle burst mode 8-cycle burst mode 4-cycle burst mode 8-cycle burst mode t RHRL RLRH Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Min Typ Max 102 ...
Page 140
... Fig 36. DC single-cycle DMA read timing in DACK-only mode. 9397 750 12337 Product data Conditions Min - 180 ASRP Conditions Min - 25 180 - - t ASRP t ASAP t APDZ t ASDV Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Typ Max Unit - 004aaa111 Typ Max Unit - ...
Page 141
... Product data Conditions Min - 25 180 - - t ASAP t ASRP t APRS t ASDV Conditions Min (min) 160 RL WL Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Typ Max Unit - APDZ 004aaa113 Typ Max Unit ...
Page 142
... (1) Programmable polarity: shown as active LOW. Fig 38. DC burst mode DMA timing. 9397 750 12337 Product data t RSIH t IHIL Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller t ILRP t IHAP 004aaa115 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 142 of 150 ...
Page 143
... Rev. 03 — 06 January 2004 Single-chip USB OTG controller detail 0.75 1.45 1 0.2 0.12 0.1 0.45 1.05 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 SOT314 ( 1.05 0 ISSUE DATE 00-01-19 03-02-25 143 of 150 ...
Page 144
... REFERENCES JEDEC JEITA MO-195 - - - Rev. 03 — 06 January 2004 Single-chip USB OTG controller detail 0.05 0.08 0.1 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 SOT543-1 y ISSUE DATE 00-11-22 02-04-09 144 of 150 ...
Page 145
... Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. Rev. 03 — 06 January 2004 Single-chip USB OTG controller 2.5 mm 350 called small/thin packages. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 3 so called 145 of 150 ...
Page 146
... Rev. 03 — 06 January 2004 Single-chip USB OTG controller Soldering method Wave not suitable [4] not suitable suitable [5][6] not recommended [7] not recommended [8] not suitable © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1362 [2] Reflow suitable suitable suitable suitable suitable not suitable 146 of 150 ...
Page 147
... The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller 10 C measured in the atmosphere of the reflow © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
Page 148
... Preliminary data (9397 750 10087) 9397 750 12337 Product data Added the OTG logo. Changed reference to OTG specification from Rev.1.0 to Rev. 1.0a Table 1 and Figure 3: added type number ISP1362EE/01. Figure 1: updated. Figure 3: added index area. Table 2: updated. Section 9.7.1: updated. Section 10: added ...
Page 149
... SPARClite — registered trademark of Sparc International. StrongARM — trademark of ARM Ltd. Toshiba — registered trademark of Toshiba Corp. Rev. 03 — 06 January 2004 ISP1362 Single-chip USB OTG controller Fax: + 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 149 of 150 ...
Page 150
... Date of release: 06 January 2004 Document order number: 9397 750 12337 Single-chip USB OTG controller 13.4 DC direct memory access (DMA) transfer . . . . . . . . 54 13.5 ISP1362 DC suspend and resume . . . . . . . . . . . . . . 58 14 OTG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14.1 OtgControl register (R/W: 62H/E2H 14.2 OtgStatus register (R: 67H 14.3 OtgInterrupt register (R/W: 68H/E8H) ...