VSC8115YA Vitesse Semiconductor Corp., VSC8115YA Datasheet
VSC8115YA
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VSC8115YA Summary of contents
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Target Specification VSC8115 Features • Performs clock and data recovery for 622.08Mb/s (STS-12/OC-12/STM-4) or 155.52Mb/s (STS-3/OC-3/STM-1) NRZ data • Meets Bellcore, ITU and ANSI Specifications for Jitter Performance • 19.44MHz reference frequency LVTTL Input • Lock Detect output pin monitors ...
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STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Functional Description The VSC8115 contains an on-chip PLL consisting of a phase/frequency detector, a loop filter using one external capacitor, a LC-based voltage-controlled oscillator (VCO), and a programmable frequency divider. The phase/frequency ...
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Target Specification VSC8115 Figure 1: Control Diagram for Signal Detection and PLL Bypass Operation 2 DATAIN+/- PLL Clock (on-chip) REFCLK STS12 BYPASS LOCKREFN SD Table 1: Signal Detection and PLL Bypass Operation Control STS12 BYPASS ...
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STS-12/STS-3 Multi Rate Clock and Data Recovery Unit AC Characteristics Table 2: Performance Specifications Parameters VCO Center Frequency CRU’s Reference Clock Frequency Tolerance OC-12/STS12 Capture Range Clock Output Duty Cycle Acquisition Lock Time OC-12/STS-12 LVDS Output Rise & Fall Times ...
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Target Specification VSC8115 Jitter Tolerance Jitter Tolerance is the ability of the Clock and Data Recovery Unit to track timing variation in the received data stream. The Bellcore and ITU specifications allow the received optical data to contain jitter. The ...
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STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Retimed Data and Clock Outputs AC Specification As indicated in figure recommended that the retimed data output be captured with the rising edge of the clock output. Data valid ...
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Target Specification VSC8115 DC Characteristics Table 4: LVPECL Single-ended Inputs and Outputs Parameters Description V Input HIGH voltage IH V Input LOW voltage IL I Input HIGH current IH I Input LOW current IL V Output LOW voltage OL V ...
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STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Table 6: LVDS Differential Outputs Parameters Description Common Mode V OCM voltage Differential V OUT Output Swing Table 7: LVPECL Differential Outputs Parameters Description Common Mode V OCM voltage Differential V OUT ...
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Target Specification VSC8115 Absolute Maximum Ratings Power Supply Voltage (V ) Potential to GND.................................................................................-0. Input Voltage (LVPECL Inputs)..................................................................................... -0. Input Voltage (LVTTL Inputs) ....................................................................................... -0. Output Current (LVDS or LVPECL Outputs).......................................................................................... ...
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STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Table 10: Pin Identification Signal I/O DATAIN+/- I DATAOUT+/- O CLKOUT+/- O STS12 I LOCKREFN REFCLK I LOCKDET O BYPASS I CAP+/CAP- I VDD VSS VDDA VSSA Page 10 ...
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Target Specification VSC8115 Package Information G52272-0, Rev. 1.1 9/29/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION TSSOP Package Drawings Key aaa b b1 bbb ...
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... Commercial Temperature ambient case VSC8115YA1 STS-12/STS-3 Multi-Rate Clock and Data Recovery Unit Pin TSSOP Extended Temperature ambient to 110 C case VSC8115YA2 STS-12/STS-3 Multi-Rate Clock and Data Recovery Unit Pin TSSOP Industrial Temperature, -40 C ambient case Notice This document contains information about a proposed product during its design phase of development and is subject to change without notice at any time ...