VSC7212RG Vitesse Semiconductor Corp., VSC7212RG Datasheet
VSC7212RG
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VSC7212RG Summary of contents
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Preliminary Data Sheet VSC7212 Features • ANSI X3T11 Compliant Fibre Channel and IEEE 802.3z Compliant Gigabit Ethernet Transceiver • Over 2Gb/s Duplex Raw Data Rate • Redundant PECL Tx Outputs and Rx Inputs • 8B/10B Encoder/Decoder, Optional Encoder/ Decoder Bypass ...
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Gigabit Interconnect Chip Notation Differential signals (i.e., PTX+ and PTX-) may be referred single signal (i.e., PTX) by dropping reference to the “+” and “- ”. REFCLK refers to the single-ended TTL or differential PECL input pair ...
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Preliminary Data Sheet VSC7212 Transmitter Functional Description Transmitter Data Bus The VSC7212 transmitter has an 8-bit input transmit data character, T(7:0), and two control inputs, C/D and WSEN. The C/D input determines whether a normal data character or a special ...
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Gigabit Interconnect Chip A similar situation exists when TBC is used to define a data eye; only the rising edges of TBC are used to define the external data timing. The internal clock active edges are placed at 90× and ...
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Preliminary Data Sheet VSC7212 8B/10B Encoder The VSC7212 contains an 8B/10B encoder which translates the 8-bit input data on T(7:0) into a 10-bit encoded data character. A C/D input is also provided which, along with KCHAR, allow the transmission of ...
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Gigabit Interconnect Chip Word Sync Generation The VSC7212 can perform chip-to-chip alignment (also referred to as “word alignment” or “word sync”), meaning that the receive data output streams from multiple chips are aligned such that the same n-byte word presented ...
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Preliminary Data Sheet VSC7212 Receiver Functional Description Serial Data Source The receiver has both primary and redundant serial input ports, PRX and RRX, respectively, which consist of differential PECL input buffers. It also has a control input, RXP/R, used to ...
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Gigabit Interconnect Chip Clock and Data Recovery The receiver has a Clock Recovery Unit (CRU) which accepts the selected serial input source, extracts the high-speed clock and retimes the data. The CRU is monolithic. The CRU automatically locks on data ...
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Preliminary Data Sheet VSC7212 Elastic Buffer and Channel De-Skewing An elastic buffer is included in the receiver. Decoded data and status information is written into these buffers with the recovered clock, and is read with the selected word clock (either ...
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Gigabit Interconnect Chip of the VSC7212 only on the rising edge of the selected word clock at 1/10th the baud rate. Timing waveforms for the output data and status are shown in Figure 6, Figure 7 and Figure 8. REFCLK ...
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Preliminary Data Sheet VSC7212 If RMODE1 is LOW and if the transmitting device’s REFCLK is not precisely frequency-locked to a receiver’s REFCLK, then the channel’s elastic buffer will tend to gradually fill or empty as the recovered clock (which is ...
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Gigabit Interconnect Chip Within the receiver there are elastic buffers used to deskew multiple VSC7212s and/or VSC7216s in order to align them to a common word clock. The receiver’s elastic buffer allows the chips’ input to be skewed up to ...
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Preliminary Data Sheet VSC7212 There are four distinct modes of operation defined in Table 6. The first row disables both word alignment and rate matching. (The fourth and fifth row configurations function identically to the first row.) The second row ...
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Gigabit Interconnect Chip Receiver State Machine The VSC7212 contains a Loss of Synchronization State Machine (LSSM) which is responsible for detecting and handling loss of bit and word clock synchronization in a controlled manner. There are three states in the ...
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Preliminary Data Sheet VSC7212 Figure 10: State Diagram of the Invalid Transmission Counter Valid 0 Mis-Aligned “Comma” Link Status Outputs On the receiver output bus, the ERR, KCH and IDLE outputs indicate status for the receiver as shown below in ...
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Gigabit Interconnect Chip Loopback Operation Loop back control pins, LBEN(1:0), are provided to internally loopback data paths for on-chip diagnosis. Both serial and parallel loopback functions are provided. Table 8: Loopback Mode Selection LBEN(1: Normal Operation 0 1 ...
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Preliminary Data Sheet VSC7212 Figure 11: Parallel Loopback Mode Operation LBEN(1:0) RXP/R LBTX Clk/Data PRX+ Recovery PRX- RRX+ RRX- PSDET RSDET RECEIVER Built-In Self Test Operation Built-In Self Test operation is enabled when the BIST input is HIGH, which causes ...
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Gigabit Interconnect Chip Compatibility with VSC7214 and VSC7211 Care has been taken in the functional definition of the VSC7212 to be sure that it is compatible with the VSC7211 and VSC7214 at the serial link level, and that the transmitter ...
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Preliminary Data Sheet VSC7212 VSC7214 MODE 1: RCLKEN=LOW, FLOCK=LOW, INDEP=HIGH Receiver R(7:0), ERR, KCH and IDLE outputs are synchronous to REFCLK, IDLE insertion/deletion is enabled. The VSC7212 should be configured with RMODE(1:0)=00, FLOCK=0, and WSI=1. The WSI connection inhibits chip-to-chip ...
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Gigabit Interconnect Chip AC Characteristics Figure 13: Transmit Input Timing Waveforms with TMODE = 000 REFCLK (DUAL=0) REFCLK (DUAL=1) Internal Clock (from PLL) T(7:0) C/D WSEN Figure 14: Transmit Input Timing Waveforms with TMODE = 10X TBC Internal Clock (from ...
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Preliminary Data Sheet VSC7212 Figure 15: Transmit Input Timing Waveforms with TMODE = 11X (“ASIC-Friendly” Timing) TBC Internal Clock (from PLL) T(7:0) C/D WSEN Table 10: Transmit Input AC Characteristics with TMODE = 11X Parameters Description Input Skew relative to ...
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Gigabit Interconnect Chip Figure 17: Receive Output Timing Waveforms with RMODE = REFCLK (DUAL = 0) REFCLK (DUAL = 1) R(7:0), TBERR KCH, IDLE, ERR PSDET, RSDET Table 12: Receive Output AC Characteristics with RMODE = 00 ...
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Preliminary Data Sheet VSC7212 Figure 19: RCLK and RCLKN Timing Waveforms with DUAL = 1 RCLK RCLKN Table 14: General Receive AC Characteristics Parameters Description Delay between rising edge of T RCLK to rising edge of 3 RCLKN RCLK to ...
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Gigabit Interconnect Chip REFCLK Table 15: Reference Clock Requirements Parameters Description FR Frequency range FO Frequency offset DC REFCLK duty cycle T ,T REFLCK and TBC pulse width REFCLK rise and fall time RCR RCF REFCLK ...
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Preliminary Data Sheet VSC7212 Figure 21: Parametric Measurement Information Serial Input Rise and Fall Time T r Receiver Input Eye Diagram Jitter Tolerance Mask Serial Output Load © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • ...
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Gigabit Interconnect Chip DC Characteristics Parameters Description TTL Outputs (R(7:0), KCH, IDLE, ERR, RCLK/RCLKN, TBERR, PSDET, RSDET, WSO, REFOUT) V TTL output HIGH voltage OH V TTL output LOW voltage OL I TTL output leakage current OZ TTL Inputs (TBC, ...
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Preliminary Data Sheet VSC7212 Absolute Maximum Ratings Power Supply Voltage (any V DDX PECL Differential Input Voltage ............................................................................................ -0. TTL Input Voltage ............................................................................................................................. -0.5V to 5.5V TTL Output Voltage .............................................................................................................. -0. TTL Output Current ...................................................................................................................................... 50mA ...
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Gigabit Interconnect Chip Package Pin Descriptions 99 97 N/C 1 PTXEN VDDP 3 PTX+ PTX- 5 VSSD RTXEN 7 VDDR RTX+ 9 RTX- VSSD 11 VDDA CAP0 13 CAP1 VSSA 15 VDDD PRX+ 17 PRX- VSSD 19 RXP/R DUAL 21 ...
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Preliminary Data Sheet VSC7212 Table 16: Pin Identification Pin Name I/O 99,98,97 T0, T1, T2 96,95,91 T3, T4 90, WSEN I 92 TBC I 86 KCHAR I 85 TMODE0 82 TMODE1 I ...
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Gigabit Interconnect Chip Pin Name I/O 66 ERR O 63 RCLK O 61 RCLKN 36 RMODE0 I 37 RMODE1 17 PRX PRX- 22 RRX RRX- 34 LBEN0 I 35 LBEN1 20 RXP PSDET O ...
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Preliminary Data Sheet VSC7212 Pin Name I/O 29 FLOCK I 27 BIST I 28 ENDEC I 38 RESETN I 39 WSI I 45 WSO O 79 TCK I 78 TMS I 77 TDI I 74 TDO O 80 TRSTN I ...
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Gigabit Interconnect Chip Package Thermal Considerations The VSC7212 is packaged in a 100-pin, 14x14x1.0mm, cavity-down, thermally-enhanced TQFP. This package uses an industry-standard EIAJ footprint but has been enhanced to improve thermal dissipation. The construction of the package is shown in ...
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Preliminary Data Sheet VSC7212 Package Information: 100-pin TQFP F G 100 TYPICAL, 8 PLACES A 0.20 Rad. Typ. 0.20 Rad. Typ. NOTES: Drawing not to scale. All units in mm unless otherwise noted. Drawing ...
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... Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE ESE SEMICONDUCTOR CORPORATION SEMICONDUCTOR CORPORATION VSC7212 RG Package RG: 100-Pin TQFP, 14x14x1.0mm Body Figure 24: Package Marking Information VITESSE VSC7212RG #### AAAAA Internet: www.vitesse.com Preliminary Data Sheet VSC7212 Package Suffix Lot Tracking Code ( characters) G52268-0, Rev 3.3 04/10/01 ...