W312-02HT Cypress Semiconductor Corporation., W312-02HT Datasheet
W312-02HT
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W312-02HT Summary of contents
Page 1
... PCI9_E VDD_PCI RST# VDD_48MHz 48MHz/FS3* Note: 1. Internal 100K pull-up resistors present on inputs marked with *. De- sign should not rely solely on internal pull-up resistor to set I/O pins HIGH. 24_48MHz/FS4* • 3901 North First Street • San Jose W312-02 [ REF0/FS0 REF1/FS1 REF2 X2 4 ...
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... PCI STOP Input: This input will disable PCI0:8 and PCI9_E when it is active. I AGP STOP Input: This input will disable AGP0:2 when it is active. I REF STOP Input: This input will disable REF0:2, 24_48MHz and 48 MHz outputs when it is active. W312-02 Page [+] Feedback ...
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... Power Connection: Power supply for 48 MHz output buffers. Connect to 3.3V. P 3.3V Power Connection: Power supply for reference output buffers. Connect to 3.3V. P 3.3V Power Connection: Power supply for PLL core. Connect to 3.3V. G Ground Connections: Connect all ground pins to the common system ground plane. W312-02 Page [+] Feedback ...
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... Serial Data Interface The W312-02 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word write, byte/word read, block write and block read operations from the controller ...
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... Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits 28 Read 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop W312-02 Page [+] Feedback ...
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... W312-02 Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits Byte 1 - Bits Byte N - Bits Byte 0: Control Register 0 Bit Pin# Bit 7 – Bit 6 – ...
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... When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit. WD_PRE_SCAL 150 2.5 sec Name Default X Latched FS[4:0] inputs. These bits are read only Reserved 0 Reserved 0 SW Frequency selection bits. See Table 5. W312-02 Description Description Description Page [+] Feedback ...
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... Revision ID bit[0] 1 Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. 0 Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. 0 Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. 0 Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only. W312-02 Page [+] Feedback ...
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... Reserved 0 PCI skew control 00 = Normal –500 Reserved 11 = +500 ps 0 AGP skew control 00 = Normal –150 +150 +300 ps W312-02 Description Page [+] Feedback ...
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... The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, 0 AGP and SDRAM. When it is cleared, W312 will use the same frequency ratio 0 stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. ...
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... The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, 0 AGP and SDRAM. When it is cleared, W312-02 will use the same frequency 0 ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. 0 W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 0 MHz ...
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... Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All of the related registers are summarized inTable 7. W312-02 PLL Gear Constants PCI (G) 39 ...
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... The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the pre- scaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit. WD_PRE_SCALER 0 = 150 2.5 sec Document #: 38-07259 Rev. *C Description W312-02 Page [+] Feedback ...
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... M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Fixed Value for Range of N-Value Register M-Value Register for Different CPU Frequency 93 48 W312-02 97–255 127–245 Page [+] Feedback ...
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... OH Termination to V pull-up (external) Termination to V pull-up (external 1.5V OH W312-02 Rating Unit –0.5 to +7.0 V –65 to +150 °C –55 to +125 ° +70 °C 2 (min.) kV Min. Typ. Max. Unit 260 GND – 0.3 0 –25 µ ...
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... Notes: 5. The W312-02 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). ...
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... Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. W312-02 Min. Typ. Max. Unit ...
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... CPUDriver R9 CPUCLK_C 47 Figure 1. K7 Open Drain Clock Driver Test Circuit Ordering Information Ordering Code W312-02H 48-pin SSOP W312-02HT 48-pin SSOP - Tape and Reel Lead-free CYW312OXC 48-pin SSOP CYW312OXCT 48-pin SSOP - Tape and Reel Document #: 38-07259 Rev. *C Test Condition/Comments Determined by PLL divider ratio (see m/n below) (24.004 – ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. W312-02 51-85061-*C ...
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... Document History Page Document Title: W312-02 FTG for VIA™ K7 Series Chipset with Programmable Output Frequency Document Number: 38-07259 Issue REV. ECN NO. Date ** 110524 01/07/02 *A 118014 09/13/02 *B 122860 12/19/02 *C 358435 See ECN Document #: 38-07259 Rev. *C Orig. of Change Description of Change SZV Change from Spec number: 38-01087 to 38-07259 RGL Changed the KT266 word to K7 Series in the title and features in page 1 ...