PALLV22V10-7JC Lattice Semiconductor Corp., PALLV22V10-7JC Datasheet
PALLV22V10-7JC
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PALLV22V10-7JC Summary of contents
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... The PALLV22V10 is an advanced PAL erasable CMOS technology. The PALLV22V10Z provides low voltage and zero standby power µA maximum standby current, the PALLV22V10Z allows battery powered operation for an extended period. The PALLV22V10 device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fi ...
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... Product terms with all connections opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. The PALLV22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four potential output configurations; registered output or combinatorial I/O, active high or active low (see Figure 2). The confi ...
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... Variable Input/Output Pin Ratio The PALLV22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to V Registered Output Configuration Each macrocell of the PALLV22V10 includes a D-type flip-flop for data storage and synchronization. ...
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... Preset/Reset For initialization, the PALLV22V10 has additional preset and reset product terms. These terms are connected to all registered outputs. When the synchronous preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. ...
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... Note that preset and reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. Benefits of Lower Operating Voltage The PALLV22V10 has an operating voltage range of 3 3.6 V. Low voltage allows for lower operating power consumption, longer battery life, and/or smaller batteries for notebook applications. ...
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... This feature results in considerable power savings for operation at low to medium frequencies. Product-Term Disable On a programmed PALLV22V10Z, any product terms that are not used are disabled. Power is cut off from these product terms so that they do not draw current. Product-term disabling results in considerable power savings. This saving is greater at the higher frequencies. ...
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... (13 GND 12 (14 PALLV22V10 and PALLV22V10Z Families 24 (28 I (27 I/O D ...
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... V OUT = Max (Note 2) V OUT = Max (Note 2) V OUT = 0 Max (Note 3) Outputs MHz, Open (I OUT = 0 mA) PALLV22V10 - 7/10/15 (Com’l), -15 (Ind’ ° +75 ° with -40 ° +85 °C A ...
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... CF MAX S Test Condition 2 3 25°C V OUT = 2 MHz 1/( 1/( (Note 3) 1/( can be found using the following equation: CF PALLV22V10 - 7/10/15 (Com’l), -15 (Ind’l) Typ Unit -10 -15 Min Max Min Max Min Max 7.5 ...
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... (Note 2) V OUT = Max (Note 2) V OUT = 0 Max (Note MHz Outputs Open (I OUT = 0 mA Max (Note MHz CC vs. Frequency graph in this datasheet for typical CC PALLV22V10Z- -40°C to +85°C A Min Max Unit 2 -0.3 V 0.4 V ...
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... Test Condition 2 OUT = 2.0 V Parameter Description LOW HIGH External Feedback 1/( Internal Feedback (f CNT ) 1/( (Note 4) No Feedback 1/( can be found using the following equation PALLV22V10Z-25 Typ Unit 3 25° MHz 1 -25 Min Max Unit 25 ns ...
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... Registered Output 18956D-007 Input V T Output t WL 18956D-009 Input Asserting V T Synchronous Preset V T Clock t ARR Registered V T Output 18956D-011 PALLV22V10 and PALLV22V10Z Families 18956D-008 b. Registered output 0. 0.5V 18956D-010 d. Input to output disable/enable ...
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... Line is High- Impedance “Off” State VCC Test Point Closed L: Open 1.6K Z: Closed Open PALLV22V10 and PALLV22V10Z Families 18956D-013 18956D-014 Measured R 2 Output Value ...
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... By utilizing 50% of the device, a midpoint is defined for I to estimate the I requirements for a particular design Frequency (MHz vs. Frequency . From this midpoint, a designer may scale the I CC PALLV22V10 and PALLV22V10Z Families PALLV22V10-7 PALLV22V10-10/ 18956D-015 graphs up or down CC ...
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... N Min Reprogramming Cycles ROBUSTNESS FEATURES The PALLV22V10 has some unique features that make it extremely robust, especially when operating in high speed design environments. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns ...
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... PR Power-Up Reset Time t S Input or Feedback Setup Time t WL Clock Width LOW 2.7 V Power Registered Active-Low Output Clock 16 Parameter Description Figure 3. Power-Up Reset Waveform PALLV22V10 and PALLV22V10Z Families can rise CC Max Unit 1000 ns See Switching Characteristics V CC 18956D-018 ...
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... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant tem- perature. Therefore, the measurements can only be used in a similar environment. Parameter Description 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air PALLV22V10 and PALLV22V10Z Families Typ SKINNY DIP PLCC Unit 26 20 ° ...
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... Supply Voltage 18956D-002 PALLV22V10 and PALLV22V10Z Families PLCC GND/ I/O 2 18956D-003 ...
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... The Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice/Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations. PALLV22V10 and PALLV22V10Z Families C OPERATING CONDITIONS C = Commercial (0°C to +75° Industrial (-40° ...