PALCE16V8H-7JC Lattice Semiconductor Corp., PALCE16V8H-7JC Datasheet
PALCE16V8H-7JC
Available stocks
Related parts for PALCE16V8H-7JC
PALCE16V8H-7JC Summary of contents
Page 1
DISTINCTIVE CHARACTERISTICS Pin and function compatible with all 20-pin PAL Electrically erasable CMOS technology provides reconfigurable logic and full testability High-speed CMOS technology — 5-ns propagation delay for “-5” version — 7.5-ns propagation delay for “-7” version Direct plug-in replacement ...
Page 2
BLOCK DIAGRAM MACRO MACRO MACRO I/O I FUNCTIONAL DESCRIPTION The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the PALCE16V8. It has all the architectural ...
Page 3
Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the PALCE16V8 device code. This option allows full utilization of the macrocell SG1 *In macrocells MC and MC , SG1 ...
Page 4
Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0 configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1 The flip-flop is loaded on ...
Page 5
Programmable Output Polarity The polarity of each macrocell can be active-high or active-low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), ...
Page 6
CLK a. Registered active low c. Combinatorial I/O active low Combinatorial output active low Notes: 1. Feedback is not available on pins 15 and 16 in the combinatorial output mode. 2. This configuration ...
Page 7
Power-Up Reset All flip-flops power logic LOW for predictable system initialization. Outputs of the PALCE16V8 will depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial ...
Page 8
The current will go to almost zero (I maintain the states held before the device went into the standby mode. There is no speed penalty associated with coming out of standby mode. When any input ...
Page 9
LOGIC DIAGRAM CLK ...
Page 10
LOGIC DIAGRAM (CONTINUED ...
Page 11
... 0 Max (Note 3) OUT CC Outputs Open ( mA), V OUT V = Max CC Outputs Open ( mA), OUT V = Max MHz CC and I (or I and I ). OZL IH OZH PALCE16V8H-5/7 (Com’ Min Max , V = Min 2 Min 0.5 CC 2.0 0.8 10 –100 10 –100 –30 –150 = 125 115 ...
Page 12
... S CF 1/( and t are defined under best case conditions. Future process improvements PZX PXZ EA ER can be found using the following equation: CF PALCE16V8H-5/7 (Com’l) Typ Unit 5 ° MHz Min Max Min Max ...
Page 13
... Max OUT (Note 0 Max (Note 3) OUT CC Outputs Open ( mA) OUT V = Max MHz CC and I (or I and I ). OZL IH OZH PALCE16V8H-10 (Com’l, Ind Operating Min Max , V = Min 2 Min 0.5 CC 2.0 0.8 10 –100 10 –100 –30 –150 115 ...
Page 14
... CF 1/( and t are defined under best case conditions. Future process improvements PZX PXZ EA ER can be found using the following equation: CF PALCE16V8H-10 (Com’l, Ind) Typ Unit 5 ° MHz 8 pF -10 2 Min Max Unit ...
Page 15
ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...
Page 16
CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...
Page 17
... Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second 0.5 V has been chosen to avoid test problems caused by tester ground degradation. OUT PALCE16V8H-15/25 (Com’l, Ind), Q-15/25 (Com’l), Q-20/25 (Ind) OPERATING RANGES Commercial (C) Devices Ambient Temperature (T Operating in Free Air . . . . . . . . . . . . . . . 0° ...
Page 18
... These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected calculated value and is not guaranteed 1/f (internal feedback) – MAX S 18 PALCE16V8H-15/25 (Com’l, Ind), Q-15/25 (Com’l), Q-20/25 (Ind) Test Conditions 2 5 °C, V OUT = 2 MHz -15 -20 Min Max Min 15 12 ...
Page 19
ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...
Page 20
CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...
Page 21
ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...
Page 22
CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...
Page 23
ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...
Page 24
CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...
Page 25
SWITCHING WAVEFORMS Input or V Feedback Combinatorial Output a. Combinatorial output t WH Clock c. Clock width Output Notes 1 Input pulse amplitude 3 Input rise ...
Page 26
KEY TO SWITCHING WAVEFORMS WAVEFORM SWITCHING TEST CIRCUIT Specification Closed Open Closed H Z: Open Closed 26 INPUTS OUTPUTS Must be Will be ...
Page 27
TYPICAL I CHARACTERISTICS 25° 150 125 100 The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, ...
Page 28
ENDURANCE CHARACTERISTICS The PALCE16V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts result, the device can be erased and reprogrammed—a feature which ...
Page 29
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8Z ESD Input Protection Transition and Detection Clamping POWER-UP RESET The PALCE16V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will ...
Page 30
V Power Registered Output Clock TYPICAL THERMAL CHARACTERISTICS Measured ambient. These parameters are not tested. Parameter Symbol Parameter Description Thermal impedance, junction to case jc Thermal impedance, junction to ambient ja Thermal impedance, junction to ambient ...
Page 31
CONNECTION DIAGRAMS Top View DIP/SOIC CLK ...
Page 32
... PALCE16V8H-5 JC PALCE16V8H-7 PC, JC, SC PALCE16V8H-10 PC, JC, SC, PI, JI PALCE16V8Q-10 JC PALCE16V8H-15 PC, JC, SC PALCE16V8Q-15 PC, JC PALCE16V8Q-20 PI, JI PALCE16V8H-25 PC, JC, SC, PI, JI PALCE16V8Q-25 PC, JC, PI, JI PALCE16V8Z-12 PI, JI PALCE16V8Z-15 PALCE16V8Z-25 PC, JC, SC, PI, JI Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local Lattice/ /5 Vantis sales offi ...