CY7C63101-SC Cypress Semiconductor Corporation., CY7C63101-SC Datasheet
CY7C63101-SC
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CY7C63101-SC Summary of contents
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... CY7C63000 CY7C63001 CY7C63100 CY7C63101 CY7C63200 CY7C63201 Universal Serial Bus Microcontroller Cypress Semiconductor Corporation PRELIMINARY • 3901 North First Street • San Jose fax id: 3401 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 • CA 95134 • 408-943-2600 October 1996 - Revised June 26, 1997 ...
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... USB Enumeration Process ................................................................................................................ 18 5.9.2 End Point 0 .......................................................................................................................................... 18 5.9.2.1 End Point 0 Receive .................................................................................................................................... 18 5.9.2.2 End Point 0 Transmit ................................................................................................................................... 18 5.9.3 End Point 1 .......................................................................................................................................... 20 5.9.3.1 End Point 1 Transmit ................................................................................................................................... 20 5.9.4 USB Status and Control ..................................................................................................................... 20 5.10 Instruction Set Summary ..........................................................................................................21 6.0 ABSOLUTE MAXIMUM RATINGS ...............................................................................................22 7.0 DC CHARACTERISTICS ..............................................................................................................22 8.0 SWITCHING CHARACTERISTICS ...............................................................................................23 9.0 ORDERING INFORMATION .........................................................................................................24 10.0 PACKAGE DIAGRAMS ..............................................................................................................25 PRELIMINARY TABLE OF CONTENTS 2 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 ...
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... Figure 5-25. USB Status and Control Register (Address 0x13)...................................................... 20 Figure 8-1. Clock Timing .................................................................................................................... 24 Figure 8-2. USB Data Signal Timing.................................................................................................. 24 Table 5-1. I/O Register Summary......................................................................................................... 9 Table 5-2. Output Control Truth Table ..............................................................................................13 Table 5-3. Interrupt Vector Assignments..........................................................................................16 Table 5-4. Instruction Set Map ...........................................................................................................21 2 PRELIMINARY TABLE OF FIGURES TABLE OF TABLES 3 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 ...
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... USB optimized instruction set • Internal memory — 128 bytes of RAM — 2K bytes of EPROM (CY7C63000, CY7C63100, CY7C63200) — 4K bytes of EPROM (CY7C63001, CY7C63101, CY7C63201) • I/O ports — Integrated USB transceivers — Schmitt trigger I/O pins with internal pull-up — I/O pins with LED drive capability — ...
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... DIP/SOIC/ Windowed CerDIP P0.4 P0 P0.1 2 P0.5 P0.6 P0 P0 P1.1 P1 P1.2 P1 VSS VPP VCC CEXT XTALIN 10 11 XTALOUT 5 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 PORT 1 P1.0–P1.7 24-pin SOIC/ Windowed CerDIP P0 P0.5 P0 P0.7 P1.1 P1 P1.3 P1 P1.5 P1 P1.7 P1 VSS 9 15 D– ...
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... Crystal / Ceramic resonator in or external clock input 11 13 Crystal / Ceramic resonator out Connects to external R/C timing circuit for optional suspend 9 11 wakeup 14 16 USB data USB data– Programming voltage supply, tie to ground during normal 8 10 operation 12 14 Voltage supply 7 9 Ground 6 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 ...
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... The 14-bit Program Counter (PC) is capable of addressing 16K bytes of program space. However, the program space of the CY7C63000, CY7C63100 and CY7C63200 is 2K bytes. For applications requiring more program space, the CY7C63001, CY7C63101 and CY7C63201 each offer 4K bytes of EPROM. The program memory space is divided into two functional groups: Interrupt Vectors and program code. ...
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... Interrupt Vector - 1.024 ms 0x0006 Interrupt Vector - USB Endpoint 0 0x0008 Interrupt Vector - USB Endpoint 1 0x000A Reserved 0x000C Interrupt Vector - GPIO 0x000E Interrupt Vector - Cext 0x0010 On-chip program Memory 0x07FF 2K ROM (CY7C63000, CY7C63100,CY7C63200) 0x0FFF 4K ROM (CY7C63001, CY7C63101, CY7C63201) Figure 5-1. Program Memory Space CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 8 ...
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... Pull-up resistor control for Port 0 pins 0x09 W Pull-up resistor control for Port 1 pins 0x10 R/W USB End Point 0 transmit configuration 0x11 R/W USB End Point 1 transmit configuration 0x12 R/W USB device address 0x13 R/W USB status and control 0x14 R/W USB End Point 0 receive status 9 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 Function ...
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... Isink register for each pin. Address of the Isink register for pin 0 is located at 0x38 and the register address for pin 3 is located at 0x3B 0xFF R/W Processor status and control 4 3 R/W R/W Power-on Suspend Reset 10 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 Function R/W Reserved Reserved Run ...
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... The timer generates two interrupts: the 128 s interrupt and the 1.024 ms interrupt Count 7 Count 6 Count 5 PRELIMINARY 8.192 ms Execution begins at Reset Vector 0X00 Figure 5-4. Watch Dog Reset (WDR Count 4 Count 3 Figure 5-5. Timer Register (Address 0x23) 11 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 Count 2 Count 1 Count 0 ...
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... I/O line. The Port Isink Register is used to control the output current level and it is described later in this section. Table 5-2 is the Output Control truth table. PRELIMINARY Figure 5-6. Timer Block Diagram R/W R/W P0.4 P0 R/W R/W P1.4 P1.3 12 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 1.024 ms interrupt 128 s interrupt crystal clock Timer Register 2 1 R/W R/W R/W P0.2 P0.1 P0 R/W R/W R/W P1.2 P1 ...
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... Figure 5-9. Block Diagram of an I/O Line Port Pull-up Register Pull P0.4 Pull P0 Pull P1.4 Pull P1.3 13 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 GPIO Pin Output at I/O Pin Sink Current (‘0’) Sink Current (‘0’) Pull-up Resistor (‘1’) Hi Pull P0.2 Pull P0.1 Pull P0.0 2 ...
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... XTALIN and XTALOUT are the crystal oscillator pins MHz crystal or ceramic resonator should be connected to these pins.The feedback capacitors and bias resistor are internal to the IC. fxtal PRELIMINARY Isink4 Isink3 Reserved Reserved XTALOUT XTALIN Figure 5-14. Clock Oscillator On-chip Circuit 14 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 Isink2 Isink1 Isink0 R/W Reserved Reserved Cext ...
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... CLR Q 128 s IRQ Enable [ CLR 1 ms IRQ End P0 CLR End P0 IRQ End P1 CLR End P1 IRQ GPIO CLR GPIO IRQ Q Enable [6] CEXT Wake-up IRQ Enable [7] 15 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 R/W R/W R/W 1.024 ms 128 us Reserved Interrupt Interrupt Enable Enable IRQ Interrupt Vector Interrupt ...
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... W W P0.4 Int En P0.3 Int P1.4 Int En P1.3 Int En 16 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 Function Reset 128 s timer interrupt 1.024 ms timer interrupt USB end point 0 interrupt USB end point 1 interrupt Reserved GPIO interrupt Wake-up interrupt P0.2 Int En P0.1 Int En P0.0 Int En ...
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... It also determines token type, checks address and endpoint values, generates and checks CRC values and controls the flow of data bytes between the bus and the End Point FIFOs. PRELIMINARY 12-Input OR Gate CLR Global GPIO Interrupt Enable 17 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 GPIO Interrupt Flip Flop CLR IRQ Interrupt Priority Interrupt Encoder ...
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... While the data following a SETUP is being received by the USB engine, this bit will not be cleared by an I/O write. User firmware writes to the USB FIFOs are disabled when bit 0 is set. This prevents SETUP data from being overwritten. PRELIMINARY R/W R/W ADR4 ADR3 R/W R Count 0 Data Toggle 18 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 R/W R/W R/W ADR2 ADR1 ADR0 R/W R/W R/W IN OUT ...
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... OUT Valid No OUT Error No OUT Status No OUT N/Status No OUT Error R/W R/W Data Invalid Count 3 19 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 USB Engine Response Toggle Count Interrupt Update Update Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ...
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... End Point 0 FIFO and the USB engine responds with an ACK. If this bit is 0, data will not be written to the FIFO and the response is a NAK. This bit is cleared following a SETUP or OUT transaction. PRELIMINARY R/W R/W End Point 1 Count 3 Enable R/W R/W Enable Outs StatusOuts 20 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 R/W R/W R/W Count 2 Count 1 Count R/W R/W Reserved Force Bus Activity Resume ...
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... CPL 1B 6 ASL 1C 4 ASR 1D 5 RLC 1E 13 RRC 1F 4 RET JNC Ax 5 JACC Bx 5 INDEX 21 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address ...
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... Vrst CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 +150 +70 +0.5V CC +0.5V CC Conditions Oscillator off, D– > Voh min 5.0V, ceramic resonator cc NOTE [2, 6] linear ramp Vrst CC [3, 4] 15k ± Gnd NOTE 4 [4] Vout = 2.0 V DC, Port 0 only [4] Vout = 2 ...
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... V Description [ [ drops below Vrst, POR will not re-occur. V must return to 0.0V before POR will be re-applied on a subsequent CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 Conditions Full scale transition [9] Vout = 2.0V Summed over all Port 1 bits Per pin [7] All ports and Cext [8] All ports and Cext V = Min ...
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... CLOCK D D 9.0 Ordering Information EPROM Ordering Code Size CY7C63000-PC 2KB 12 CY7C63000-SC 2KB 12 CY7C63001-PC 4KB 12 CY7C63001-SC 4KB 12 CY7C63001-WC 4KB 12 CY7C63100-SC 2KB 16 CY7C63101-SC 4KB 16 CY7C63101-WC 4KB 16 CY7C63200-PC 2KB 10 CY7C63201-PC 4KB 10 CY7C63201-WC 4KB 10 Document #: 38-00557-D PRELIMINARY t CYC Figure 8-1. Clock Timing t r 90% ...
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... Package Diagrams 20-Lead (300-Mil) Windowed CerDIP W6 PRELIMINARY MIL-STD-1835 D-8 Config. A 18-Lead (300-Mil) Molded DIP 25 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 ...
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... Package Diagrams (continued) PRELIMINARY 20-Lead (300-Mil) Molded DIP 20-Lead (300-Mil) Molded SOIC 26 CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 24-Lead (300-Mil) Molded SOIC MIL-STD-1835 D-9 Config. A CY7C63000/CY7C63001 CY7C63100/CY7C63101 CY7C63200/CY7C63201 ...