CY7C43646AV-10AC Cypress Semiconductor Corporation., CY7C43646AV-10AC Datasheet

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... First-In First-Out (FIFO) memories with three independent ports (one bidirec- tional ×36, and two unidirectional ×18) • 1K ×36/×18×2 (CY7C43646AV) • 4K ×36/×18×2 (CY7C43666AV) • 16K ×36/×18×2 (CY7C43686AV) • 0.25-micron CMOS for optimum speed/power • ...

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... CY7C43646AV 90 89 CY7C43666AV CY7C43686AV CY7C43646AV CY7C43666AV CY7C43686AV CLKB PRS2 GND MBC RT1 SIZEB GND ...

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... CY7C43646/66/86AV- –7 –10 133 100 CY7C43646AV CY7C43666AV 1K × 36/×18 ×2 4K × 36/×18 ×2 128 TQFP 128 TQFP CY7C43646AV CY7C43666AV CY7C43686AV CY7C43646/66/86AV –15 Unit 66.7 MHz CY7C43686AV 16K × 36/×18 ×2 ...

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... ORB indicates the presence of valid data on B available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB. ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to Read or Write data on Port A. RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to Read data from Port B. CY7C43646AV CY7C43666AV CY7C43686AV outputs, 0–35 outputs, 0– ...

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... When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X and Y registers. The number of bit Writes required to program the offset registers is 40 for the CY7C43646AV, 48 for the CY7C43666AV, and 56 for the CY7C43686AV. The first bit Write stores the Y-register MSB and the last bit Write stores the X-register LSB ...

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... A HIGH selects a Write operation and a LOW selects a Read operation on Port A for a LOW-to-HIGH transition of CLKA. The A state when W/RA is HIGH. WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C. CY7C43646AV CY7C43666AV CY7C43686AV outputs are in the HIGH impedance 0–35 Page ...

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... Port B. A HIGH on the BE/FWFT input when the Master Reset (MRS1 and MRS2) inputs go from LOW to HIGH will select a Big Document #: 38-06026 Rev. *C CY7C43646AV CY7C43666AV CY7C43686AV Endian arrangement. When data is moving in the direction from Port A to Port B, the most significant byte (word) of the long- word written to Port A will be transferred to Port B first ...

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... Valid programming values for the registers range from 0 to 1023 for the CY7C43646AV 4095 for the CY7C43666AV 16383 for the CY7C43686AV (see note 61). After all the offset registers are programmed from Port A, the Port C Full/Input Ready (FFC/IRC) is set HIGH and both FIFOs begin normal operation ...

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... When sending data from Port C to Port A via the Mail2 Register, the following is the case: A LOW-to-HIGH transition on CLKC writes C C Write is selected by WENC with MBC HIGH. If the selected Port C bus size is 18 bits, then the usable width of the Mail2 CY7C43646AV CY7C43666AV CY7C43686AV or greater after SKEW2 ...

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... Write pointer. Flags are governed by the relative locations of the Read and Write pointers and are updated during a retrans- mit cycle. Data written to the FIFO after activation of RT1, (RT2) are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. CY7C43646AV CY7C43666AV CY7C43686AV and B . When a byte-size bus is 0– ...

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... Read from FIFO1 0–8 9–17 2nd: Read from FIFO1 0–8 9–17 3rd: Read from FIFO1 0–8 9–17 4th: Read from FIFO1 A (D) BYTE SIZE - LITTLE ENDIAN CY7C43646AV CY7C43666AV CY7C43686AV Write to FIFO1 Page [+] Feedback ...

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... C 9–17 0–8 1st: Write to D FIFO2 C C 0–8 9–17 2nd: Write to FIFO2 9–17 0–8 3rd: Write to FIFO2 9–17 0–8 4th: Write to A FIFO2 (D) BYTE SIZE - LITTLE ENDIAN CY7C43646AV CY7C43666AV CY7C43686AV Read from FIFO2 Page [+] Feedback ...

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... In high-impedance state X Active, FIFO1 output register Active, FIFO1 output register X Active, Mail1 register Active, Mail1 register C 0–17 In high-impedance state In high-impedance state In high-impedance state Active, Mail1 register CY7C43646AV CY7C43666AV CY7C43686AV [1] [2] X2 and Y2 Registers Parallel programming via Port A Serial programming via SD ...

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... H (Y2 + 1)] (16384 – Y2 16383 16384 H Data Written to FIFO2 9–17 0–8 27– CY7C43646AV CY7C43666AV CY7C43686AV Synchronized to CLKA AEB AFA FFA/IRA Synchronized to CLKC AEA AFC ...

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... Data Written to FIFO1 18–26 9–17 0– Data Written to FIFO1 18–26 9–17 0– CY7C43646AV CY7C43666AV CY7C43686AV 18–26 9–17 0– Read No. Data Read From FIFO1 B B 9–17 0– ...

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... CY7C43646/66/86AV Test Conditions Min 3.0V –2 3.0V 8 Max < V < Commercial Industrial Commercial Industrial Test Conditions MHz 3. CY7C43646AV CY7C43666AV CY7C43686AV [14 3.3V ± 10% 3.3V ± 10% Max. Unit 2.4 V 0 0 ...

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... ALL INPUT PULSES 3.0V 10% GND 3 ns 7C43646/ 66/86AV Min. 7.5 3.5 3.5 before CLKC 3 0– after CLKC 0 0– CY7C43646AV CY7C43666AV CY7C43686AV 90% 90% 10 90% 90% 10 7C43646/ 7C43646/ 66/86AV 66/86AV –7 –10 –15 Max. Min. Max. Min. Max. Unit 133 100 67 ...

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... Active and CSB LOW 1 0–35 at High Impedance 1 0–35 at High Impedance 0–17 90 outputs are active and MBB is HIGH. outputs are active and MBA is HIGH. CY7C43646AV CY7C43666AV CY7C43686AV 7C43646/ 7C43646/ 66/86AV 66/86AV –10 –15 Max. Min. Max. Min. Max. ...

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... MBF1 Notes: 23. PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH. 24. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW. Document #: 38-06026 Rev. *C CY7C43646AV CY7C43666AV CY7C43686AV [23, 24] t ...

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... MBF2 Notes: 25. PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH. 26. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than the case where BE/FWFT is LOW. Document #: 38-06026 Rev. *C CY7C43646AV CY7C43666AV CY7C43686AV [25, 26] t ...

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... If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW. 29. MRS2 must be HIGH during Partial Reset. 30. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than the case where BE/FWFT is LOW. Document #: 38-06026 Rev. *C CY7C43646AV CY7C43666AV CY7C43686AV [27, 28] ...

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... SEN SDH SDH SD AEA Offset (X2) LSB , then FFC/IRC may transition HIGH one cycle later than shown. SKEW1 , then FFC/IRC may transition HIGH one cycle later than shown. SKEW1 CY7C43646AV CY7C43666AV CY7C43686AV [32] t SKEW1 AEA Offset (X2) First Word to FIFO1 t WFF t WFF ...

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... ENH t t ENS ENH ENH ENH ENS ENS [36] [36 ENS ENH ENH ENS ENH ENS ENH ENS ENS DIS ENS CY7C43646AV CY7C43666AV CY7C43686AV t t ENH ENS Page [+] Feedback ...

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... Reads. 9–17 Document #: 38-06026 Rev ENH t ENH ENH Read 2 Read Read 1 Read 2 Read 3 CY7C43646AV CY7C43666AV CY7C43686AV t ENH t t ENH ENS [38] No Operation tDI t A Read 4 Read DIS A Read 4 Read 5 Page [+] Feedback ...

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... A Read 2 Read 1 CLKL ENS ENH ENS ENH Previous Data [39 [39] [39 CY7C43646AV CY7C43666AV CY7C43686AV Operation DIS Read DIS A Read ENS ENH t No Operation DIS [ DIS [39 W3 Page ...

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... CLKB cycle later than shown. Document #: 38-06026 Rev CLK t t CLKH CLKL t t [41] CLKH CLKL t t REF CLK t A CY7C43646AV CY7C43666AV CY7C43686AV [40] t REF t t ENS ENH W1 , then the transition of ORB HIGH and load SKEW1 Page [+] Feedback ...

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... CLKA edge and rising CLKB edge is less than t Document #: 38-06026 Rev CLK t t CLKH CLKL t t [43] CLKH CLKL REF REF CLK t t ENS ENH then the transition of EFB HIGH may occur one CLKB cycle later than shown. SKEW1 CY7C43646AV CY7C43666AV CY7C43686AV W1 Page [+] Feedback ...

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... CLKA cycle later than shown. Document #: 38-06026 Rev CLK t t CLKH CLKL CLKH CLKL t REF t CLK t A CY7C43646AV CY7C43666AV CY7C43686AV t REF t t ENS ENH W1 , then the transition of ORA HIGH and load SKEW1 Page [+] Feedback ...

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... CLKC edge and rising CLKA edge is less than t Document #: 38-06026 Rev CLK t t CLKH CLKL t t [47] CLKH CLKL t t REF REF t CLK ENH then the transition of EFA HIGH may occur one CLKA cycle later than shown. SKEW1 CY7C43646AV CY7C43666AV CY7C43686AV [46] W1 Page [+] Feedback ...

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... CLKB edge and rising CLKA edge is less than t Document #: 38-06026 Rev. *C Next Word From FIFO1 t t [49] CLKH CLKL t t WFF WFF t CLK t t ENS ENH ENH FIFO1 , then IRA may transition HIGH one CLKA cycle later than shown. SKEW1 CY7C43646AV CY7C43666AV CY7C43686AV [48] Page [+] Feedback ...

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... Document #: 38-06026 Rev. *C Next Word From FIFO1 [50 CLKH CLKL t t WFF WFF t CLK t t ENH ENH then the transition of FFA HIGH may occur one CLKA cycle later than shown. SKEW1 CY7C43646AV CY7C43666AV CY7C43686AV [48] Read Disabled Page [+] Feedback ...

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... Document #: 38-06026 Rev. *C Next Word From FIFO2 t t CLKH CLK t t WFF WFF t CLK t t ENH ENS t t ENH FIFO2 , then the transition of IRC HIGH may occur one CLKC cycle later than shown. SKEW1 CY7C43646AV CY7C43666AV CY7C43686AV [51] Page [+] Feedback ...

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... ENS ENH [57] t SKEW2 t PAE ( Words ( Words in FIFO1 in FIFO1 , then the transition of FFC HIGH may occur one CLKC cycle later than shown. SKEW1 CY7C43646AV CY7C43666AV CY7C43686AV [53] [55, 56, 61] X1 Words in FIFO t PAE (X1 + 2)Words in FIFO1 t t ENH ENS t t ENS ...

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... Y1) Words in FIFO1 ENH ENS ENS , then AEB may transition HIGH one CLKB cycle later than shown. SKEW2 , then AEA may transition HIGH one CLKA cycle later than shown. SKEW2 CY7C43646AV CY7C43666AV CY7C43686AV [58, 59, 61] X2 Words in FIFO t PAE (X2 + 2)Words in FIFO2 t t ENH ...

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... FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 63 Maximum FIFO Depth =1K for the CY7C43646AV, 4K for the CY7C43666AV, and 16K for the CY7C43686AV. 64. If Port B size is word or byte referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively ...

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... MDV PMR W1 (Remains valid in Mail1 Register after Read) (A are “Don’t Care” inputs). In this first case, B 0–17 18–35 (A are “Don’t Care” inputs). In this second case, B 0–8 9–35 CY7C43646AV CY7C43666AV CY7C43686AV [68] t PMF t t ENH ENS t DIS will have valid 0– ...

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... W1 (Remains valid in Mail2 Register after Read) FIFO2 Output Register . In this first case A 0–17 (C are “Don’t Care” inputs). In this second case, A 0–8 9–17 after the RT1 rising edge. RTR to update these flags. RTR CY7C43646AV CY7C43666AV CY7C43686AV [69] t PMF t t ENS ENH t DIS t ...

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... Tri Bus Synchronous FIFO Speed (ns) Ordering Code 7 CY7C43646AV-7AC 10 CY7C43646AV-10AC 15 CY7C43646AV-15AC 3.3V 4K ×36/18×2 Tri Bus Synchronous FIFO Speed (ns) Ordering Code 7 CY7C43666AV-7AC 10 CY7C43666AV-10AC 15 CY7C43666AV-15AC 3.3V 16K×36/18×2 Tri Bus Synchronous FIFO Speed (ns) Ordering Code 7 CY7C43686AV-7AC 10 CY7C43686AV-10AC 15 CY7C43686AV-15AC 10 CY7C43686AV-10AI Document #: 38-06026 Rev. *C ...

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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C43646AV CY7C43666AV ...

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... Document Title: CY7C43646AV/CY7C43666AV/CY7C43686AV 3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO Document Number: 38-06026 Issue REV. ECN NO. Date Change ** 107507 05/23/01 *A 109946 01/10/02 *B 117207 08/22/02 *C 122278 12/26/02 Document #: 38-06026 Rev. *C Orig. of Description of Change SZV Change from Spec #: 38-00778 to 38-06026 FSG Preliminary to final OOR Added footnote to retransmit timing Added note to retransmit section ...