CY7C4265-10AI Cypress Semiconductor Corporation., CY7C4265-10AI Datasheet

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CY7C4265-10AI

Manufacturer Part Number
CY7C4265-10AI
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C4265-10AI
Manufacturer:
AOS
Quantity:
15 000
Part Number:
CY7C4265-10AI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-06004 Rev. *C
Features
Logic Block Diagram
• High-speed, low-power, first-in first-out (FIFO)
• 8K x 18 (CY7C4255)
• 16K x 18 (CY7C4265)
• 0.5 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
• Low power — I
• Fully asynchronous and simultaneous read and write
• Empty, Full, Half Full, and programmable Almost Empty
• TTL compatible
• Retransmit function
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 64-pin TQFP and 64-pin STQFP
• Pin-compatible density upgrade to CY7C42X5 family
• Pin-compatible density upgrade to
memories
times)
operation
and Almost Full status flags
IDT72205/15/25/35/45
CC
WXO/HF
= 45 mA
FL/RT
RXO
WXI
RXI
RS
WCLK
EXPANSION
CONTROL
POINTER
RESET
WRITE
WRITE
LOGIC
LOGIC
WEN
3901 North First Street
OUTPUT REGISTER
THREE–STATE
REGISTER
16K x 18
8K x 18
D
ARRAY
Q
INPUT
RAM
0–17
0–17
Functional Description
The CY7C4255/65 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can
be cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and commu-
nications buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and a Write
Enable pin (WEN). When WEN is asserted, data is written into the
FIFO on the rising edge of the WCLK signal. While WEN is held
active, data is continually written into the FIFO on each cycle. The
output port is controlled in a similar manner by a free-running Read
Clock (RCLK) and a Read Enable pin (REN). In addition, the
CY7C4255/65 have an Output Enable pin (OE). The read and write
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write appli-
cations. Clock frequencies up to 100 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (WXI,
RXI), Cascade Output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V
devices should be tied to V
8K/16K x 18 Deep Sync FIFOs
• Pb-Free Packages Available
OE
RCLK
PROGRAM
REGISTER
CONTROL
POINTER
FLAG
LOGIC
FLAG
READ
READ
San Jose
REN
CC
,
SS
FF
EF
PAE
PAF
SMODE
CA 95134
.
and the FL pin of all the remaining
Revised August 2, 2005
CY7C4255
CY7C4265
408-943-2600
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CY7C4265-10AI Summary of contents

Page 1

... Features • High-speed, low-power, first-in first-out (FIFO) memories • (CY7C4255) • 16K x 18 (CY7C4265) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — • Fully asynchronous and simultaneous read and write operation • ...

Page 2

... CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. 7C4255/65-10 7C4255/65-15 100 66 0 CY7C4265 16K x18 64-pin TQFP, STQFP CY7C4255 CY7C4265 GND GND ...

Page 3

... HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Dual-Mode Pin: Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) CY7C4255 CY7C4265 /SMODE is tied ...

Page 4

... IH < V < Com’l 45 Ind 50 Com’l 10 Ind 15 Test Conditions T = 25° MHz 5.0V CC CY7C4255 CY7C4265 [2] Ambient Temperature ± 10% 0°C to +70°C 5V ± 10% –40°C to +85°C 7C42X5-25 7C42X5-35 Max. Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0.4 ...

Page 5

... [13] 12 /SMODE tied PAF(E) CY7C4255 CY7C4265 ALL INPUT PULSES 90% 90% 10% 10% ≤ 1.91V 7C42X5-25 7C42X5-35 Max. Min. Max. Min. Max. Unit 66.7 40 28.6 MHz ...

Page 6

... Programmable Almost Empty and Program- mable Almost Full Flags (Synchronous Mode only) Document #: 38-06004 Rev. *C 7C42X5-10 7C42X5-15 7C42X5-25 Min. Max. Min. Max. Min. Max. 4.5 6 CY7C4255 CY7C4265 7C42X5-35 Min. Max. Unit Page [+] Feedback ...

Page 7

... NO OPERATION t REF VALID DATA t OE [15] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4255 CY7C4265 NO OPERATION t WFF REF t OHZ Page [+] Feedback ...

Page 8

... Document #: 38-06004 Rev RSR t RSF t RSF t RSF [18] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4255 CY7C4265 [17 [19 (maximum) = either 2 FRL CLK SKEW2 Page [+] Feedback ...

Page 9

... Document #: 38-06004 Rev ENS REF REF SKEW2 t A [14 SKEW1 DATA WRITE t WFF t ENS DATA READ CY7C4255 CY7C4265 ENH [18] t FRL t REF D0 NO WRITE DATA WRITE t WFF t ENH t A NEXT DATA READ Page [+] Feedback ...

Page 10

... PAE is offset = n. Number of data words into FIFO already = n. Document #: 38-06004 Rev CLKL t t ENS ENH t HF HALF FULL + 1 OR MORE ENS t CLKL t t ENS ENH t PAE WORDS IN FIFO t PAE t ENS CY7C4255 CY7C4265 HALF FULLOR LESS n WORDS IN FIFO Page [+] Feedback ...

Page 11

... If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. 24. PAF offset = m. Number of data words written into FIFO already = 8192 − for the CY7C4255 and 16384 − for the CY7C4265. ...

Page 12

... PAF ENS ENH t ENS t CLKL t ENH t DH PAF OFFSET , then PAF may not change state until the next WCLK rising edge. SKEW3 CY7C4255 CY7C4265 FULL– M WORDS [26] IN FIFO t [30] PAF synch t SKEW3 t t ENS ENH PAE OFFSET – ...

Page 13

... WXI WCLK Notes: 31. Write to Last Physical Location. 32. Read from Last Physical Location. Document #: 38-06004 Rev CLKL t ENH t A UNKNOWN PAE OFFSET Note Note Note XIS CY7C4255 CY7C4265 PAF OFFSET PAE OFFSET Page [+] Feedback ...

Page 14

... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06004 Rev XIS t PRT t RTR . RTR to update these flags. RTR CY7C4255 CY7C4265 Page [+] Feedback ...

Page 15

... When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. CY7C4255 CY7C4265 Selection Writing to offset registers: Empty Offset Full Offset No Operation ...

Page 16

... Notes: 37 Empty Offset (Default Values: CY7C4255/CY7C4265 n = 127). 38 Full Offset (Default Values: CY7C4255/CY7C4265 n = 127). Document #: 38-06004 Rev. *C internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled ...

Page 17

... RCLK and WCLK. Figure 1 demonstrates a 36-word width by using two CY7C4255/65s. RESET (RS) 18 7C4255 7C4265 FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) CY7C4255 CY7C4265 READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) PROGRAMMABLE (PAF) EMPTY FLAG (EF) EF DATA OUT ( Page [+] Feedback ...

Page 18

... PAF PAE WXI RXI WXO RXO 7C4255 7C4265 PAF PAE WXI RXI READ CLOCK(RCLK) WXO RXO READ ENABLE(REN) 7C4255 7C4265 OUTPUT ENABLE(OE PAE PAF WXI RXI CY7C4255 CY7C4265 DATA OUT (Q) EF PAE Page [+] Feedback ...

Page 19

... NORMALIZED t vs. SUPPLY A TEMPERATURE 1.60 1.40 1.20 1. 25° 5.0V 0. 0.60 −55.00 5.00 5.50 6.00 5.00 AMBIENT TEMPERATURE (°C) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.20 1.10 1. 3. MHz 0.80 −55.00 5.00 65.00 125.00 AMBIENT TEMPERATURE (°C) CY7C4255 CY7C4265 vs. AMBIENT A 65.00 125.00 NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.75 1.50 1.25 1. 5.0V 0. 25° 3.0V IN 0.50 20.00 30.00 40.00 50.00 60.00 FREQUENCY (MHz) Page [+] Feedback ...

Page 20

... CY7C4265–10AC CY7C4265–10ASC CY7C4265–10ASXC CY7C4265–10AI CY7C4265–10AXI 15 CY7C4265–15AC CY7C4265–15AXC CY7C4265-15ASC Package Diagrams 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) A64 64-Pin Pb-Free Thin Plastic Quad Flat Pack ( 1.4 mm) A64 Document #: 38-06004 Rev. *C Package Package ...

Page 21

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C4255 CY7C4265 51-85046-*B Page ...

Page 22

... Document History Page Document Title: CY7C4255, CY7C4265 8K/16K X 18 Deep Sync FIFOs Document Number: 38-06004 Issue Orig. of REV. ECN NO. Date Change ** 106465 07/11/01 *A 122257 12/26/02 *B 252889 See ECN *C 385985 See ECN Document #: 38-06004 Rev. *C Description of Change SZV Change from Spec Number: 38-00468 to 38-06004 ...

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