CY7C372I-83JI Cypress Semiconductor Corporation., CY7C372I-83JI Datasheet
CY7C372I-83JI
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CY7C372I-83JI Summary of contents
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... F change existing logic designs while simultaneously fixing pinout assignments. The 64 macrocells in the CY7C372i are divided between four logic blocks. Each logic block includes 16 macrocells product term array, and an intelligent product term allocator. The logic blocks in the F with an extremely fast and predictable routing resource— ...
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... CLK / GND I 3.3V. CCIO CY7C372i 7C372iL-83 7C372i- CLCC TopView /SCLK I I ISR 11 ...
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... PIM regardless of its configuration. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the four logic blocks on the CY7C372i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM ...
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... OUT MHz GND Min 0. Min 2. Max Max CY7C372i Ambient V CC Temperature V CCINT 0qC to +70qC 5V r 0.25V 5V r 0.25V or 40qC to +85qC 5V r 0.5V [2] –55° 125° 0.5V Min. Typ. [5] 2.4 2.4 [5, 6] [5, 6] [5] 2.0 –0.5 – ...
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... GND 2.13V(mil) < Output Waveform Measurement Level 0. the V X 0.5V (d) Test Waveforms measured with 35-pF AC Test Load. EA CY7C372i Min. Max 44-Lead CLCC 44-Lead PLCC 2 5 Max. 100 170: (com'l) 236: (mil) ALL INPUT PULSES 90% 90% 10% 10% < ( Max ...
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... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C372i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...
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... USE ULTRA37000™ FOR ALL NEW DESIGNS [14] 7C372i-125 Min. Max. [9] 10 [9] 12 [1] 16 [9] 10 [9] 12 [1] 16 500 CY7C372i 7C372i-83 7C372i-66 7C372i-100 7C372iL-83 7C372iL-66 Min. Max. Min. Max. Min 500 500 ...
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... INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Document #: 38-03033 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS PDL ICS CY7C372i ICO SCS Page ...
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... OUTPUT LATCH ENABLE LATCH ENABLE Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Document #: 38-03033 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS t ICOL t ICS CY7C372i t PDLL Page ...
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... Switching Waveforms (continued) Output Enable/Disable INPUT OUTPUTS Ordering Information Speed (MHz) Ordering Code 125 CY7C372i-125JC 100 CY7C372i-100JC CY7C372i-100JI 83 CY7C372i-83JC CY7C372i-83JI CY7C372i-83YMB 83 CY7C372iL-83JC 66 CY7C372i-66JC CY7C372i-66JI CY7C372i-66YMB 66 CY7C372iL-66JC Document #: 38-03033 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS t ER Package Name Package Type ...
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... 10, 11 ICO 10, 11 ICS Package Diagrams Document #: 38-03033 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Subgroups Subgroups 44-Lead Plastic Leaded Chip Carrier J67 CY7C372i 51-85003-*A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS 44-Pin Ceramic Leaded Chip Carrier Y67 CY7C372i 51-80014-** Page ...
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... Document History Page Document Title: CY7C372i UltraLogic™ 64-Macrocell Flash CPLD Document Number: 38-03033 REV. ECN NO. Issue Date ** 106378 06/18/01 *A 213375 See ECN Document #: 38-03033 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Orig. of Change Decsription of Change SZV Change from Spec# 38-00498 to 38-03033 FSG Added note to title page: “ ...