CY7C371IL-83AC Cypress Semiconductor Corporation., CY7C371IL-83AC Datasheet
CY7C371IL-83AC
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CY7C371IL-83AC Summary of contents
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Features • 32 macrocells in two logic blocks • 32 I/O pins • Five dedicated inputs including two clock pins • In-System Reprogrammable (ISR™) Flash technology — JTAG interface • Bus Hold capabilities on all I/Os and dedicated inputs • ...
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Pin Configurations PLCC Top View I/O /SCLK ISR 11 EN GND 12 CLK / I I/O 15 ...
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When V connected to a 3.3V source, the input voltage levels are compatible with both 5.0V and 3.3V systems, while the output voltage levels are compatible with 3.3V systems. There will be an additional timing delay ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature 65qC to +150qC Ambient Temperature with Power Applied 55qC to +125qC Supply Voltage to Ground Potential 0.5V to +7.0V DC Voltage ...
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Inductance Parameter Description L Maximum Pin Inductance [8] Endurance Characteristics Parameter Description N Maximum Reprogramming Cycles AC Test Loads and Waveforms 238: (COM'L) 319: (MIL) 5V OUTPUT 170: (COM' 236: (MIL) INCLUDING JIG AND SCOPE (a) Equivalent ...
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Switching Characteristics Over the Operating Range Parameter Description Combinatorial Mode Parameters t Input to Combinatorial Output PD t Input to Output Through Transparent Input or PDL [1] Output Latch t Input to Output Through Transparent Input PDLL [1] and Output ...
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Switching Characteristics Over the Operating Range (continued) Parameter Description Reset/Preset Parameters t Asynchronous Reset Width RW t Asynchronous Reset Recovery Time RR t Asynchronous Reset to Output RO t Asynchronous Preset Width PW t Asynchronous Preset Recovery Time PR t ...
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Switching Waveforms (continued) Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE ...
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Switching Waveforms (continued) Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Ordering Information Speed (MHz) Ordering Code 143 CY7C371i143AC CY7C371i143JC 110 CY7C371i110AC CY7C371i110JC CY7C371i–110AI CY7C371i–110JI Document #: 38-03032 Rev. *A USE ULTRA37000™ ...
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... CY7C371i83JC CY7C371i83AI CY7C371i83JI CY7C371iL83AC CY7C371iL83JC CY7C371iL83AI CY7C371iL83JI 66 CY7C371i66AC CY7C371i66JC CY7C371i66AI CY7C371i66JI CY7C371iL66AC CY7C371iL66JC CY7C371iL66AI CY7C371iL66JI Package Diagrams Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Package Name Package Type A44 44-Lead Thin Plastic Quad Flat Pack J67 44-Lead Plastic Leaded Chip Carrier ...
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Package Diagrams (continued) F 370, F 370i, ISR, UltraLogic, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor LASH LASH Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Document #: ...
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Document History Page Document Title: CY7C371i UltraLogic™ 32-Macrocell Flash CPLD Document Number: 38-03032 REV. ECN NO. Issue Date ** 106377 06/18/01 *A 213375 See ECN Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Orig. of Change SZV ...