CY7C185 Cypress Semiconductor Corporation., CY7C185 Datasheet

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CY7C185

Manufacturer Part Number
CY7C185
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Features
Selection Guide
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. *C
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
High speed
Fast t
Low active power
Low standby power
CMOS for optimum speed/power
Easy memory expansion with CE
TTL-compatible inputs and outputs
Automatic power down when deselected
Available in non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin
(300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded
DIP
Logic Block Diagram
15 ns
715 mW
85 mW
DOE
Description
CE
CE
WE
OE
1
2
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
1
, CE
2
and OE features
COLUMN DECODER
INPUT BUFFER
ARRAY
198 Champion Court
8K x 8
POWER
DOWN
130
-15
Functional Description
The CY7C185
organized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
chip enable (CE
tri-state drivers. This device has an automatic power down
feature (CE
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
inputs are both LOW and CE
input/output pins (IO
location addressed by the address present on the address pins
(A
selecting the device and enabling the outputs, CE
active LOW, CE
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on the
eight data input or output pins.
The input or output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH. A die coat is used to insure alpha immunity.
15
15
0
through A
64-Kbit (8K x 8) Static RAM
1
San Jose
or CE
IO
IO
IO
IO
IO
IO
IO
IO
[1]
12
0
1
2
3
4
5
6
7
2
2
). Reading the device is accomplished by
), and active LOW output enable (OE) and
is a high-performance CMOS static RAM
active HIGH, while WE remains inactive or
2
), reducing the power consumption by 70%
0
,
through IO
CA 95134-1709
110
-20
20
15
Pin Configurations
GND
IO
IO
IO
A
A
A
NC
A
A
A
A
A
A 9
10
11
12
4
5
6
7
8
0
1
2
2
DIP/SOJ
is HIGH, data on the eight data
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
7
) is written into the memory
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Revised March 25, 2008
V
WE
CE
A
A
A
OE
A
CE
IO
IO
IO
IO
IO
CC
3
2
1
0
1
2
1
7
6
5
4
3
), an active HIGH
CY7C185
100
-35
408-943-2600
35
15
1
1
and WE
and OE
[+] Feedback

Related parts for CY7C185

CY7C185 Summary of contents

Page 1

... LOW chip enable (CE chip enable (CE tri-state drivers. This device has an automatic power down feature (CE 1 when deselected. The CY7C185 standard 300-mil-wide DIP, SOJ, or SOIC package. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE inputs are both LOW and CE ...

Page 2

... I CC ≤ – 130 , 40 ≤ – 0.3V, CC – 0.3V or Test Conditions T = 25° MHz 5.0V CC CY7C185 Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° 5V ± 10% – +85 C –20 –35 Min Max Min Max 2.4 2.4 0.4 0.4 2 0.3V 2 ...

Page 3

... LZCE1 LZCE2 LOW, CE HIGH, and WE LOW. All 3 signals must be active to initiate a write and either 1 2 CY7C185 ALL INPUT PULSES 90% 90% 10% 10% ≤ THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V -20 -35 Min ...

Page 4

... LOW, CE HIGH and WE LOW going HIGH or CE going LOW. The data input setup and hold timing must be referenced to the rising 1 2 CY7C185 DATA VALID t HZOE t HZCE HIGH IMPEDANCE t PD ICC 50% ISB and WE must be LOW and CE must be HIGH ...

Page 5

... The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t Document #: 38-05043 Rev SCEI SCE2 t PWE t SD DATA VALID SCE1 SA t SCE2 DATA VALID IN and t HZWE CY7C185 [9,11 [11,12,13 Page [+] Feedback ...

Page 6

... SA WE DATA IO NOTE 12 t HZWE Note 14 goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state Document #: 38-05043 Rev. *C [11,12,13,14 SCE1 t SCE2 DATA VALID IN CY7C185 LZWE Page [+] Feedback ...

Page 7

... AMBIENT TEMPERATURE (°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4. =25°C A 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) CY7C185 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 V =5. =25° 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE ...

Page 8

... Read A8 Write A9 Deselect A10 A11 A12 Package Name Package Type 51-85031 28-pin (300-Mil) Molded SOJ 51-85014 28-pin (300-Mil) Molded DIP (Pb-free) 51-85026 28-pin (300-Mil) Molded SOIC CY7C185 Address Pin Function Number ...

Page 9

... MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES 4. PACKAGE WEIGHT 0.85gms * 0.394[10.01] 0.419[10.64] 0.026[0.66] 0.032[0.81] SEATING PLANE 0.092[2.33] 0.105[2.67] 0.004[0.10] * CY7C185 DIMENSIONS IN INCHES [MM] MIN. MAX. REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms 0.290[7.36] 0.325[8.25] 0.009[0.23] 3° MIN. 0.012[0.30] 0.310[7.87] 0.385[9.78] 51-85014-*D MIN ...

Page 10

... A 0.050 TYP. Document #: 38-05043 Rev. *C PIN 0.291 0.330 0.300 0.350 28 OPTION 1 SEATING PLANE 0.120 0.140 0.004 0.025 MIN. CY7C185 A DETAIL EXTERNAL LEAD DESIGN 0.026 0.032 0.013 0.014 0.019 0.020 OPTION 2 0.007 0.013 0.262 0.272 51-85031-*C Page [+] Feedback ...

Page 11

... Document History Page Document Title: CY7C185, 64-Kbit ( Static RAM Document Number: 38-05043 Issue REV. ECN NO. Date ** 107145 09/10/01 *A 116470 09/16/02 *B 486744 See ECN *C 2263686 See ECN VKN/AESA Removed 25 ns speed bin © Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...

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