CY7C1361A-117AI Cypress Semiconductor Corporation., CY7C1361A-117AI Datasheet
CY7C1361A-117AI
Related parts for CY7C1361A-117AI
CY7C1361A-117AI Summary of contents
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... The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The TA package version does not offer the JTAG capability. The CY7C1361A and CY7C1363A operate from a +3.3V power supply. All inputs and outputs are LVTTL-compatible. 7C1361A-150 7C1361A-133 ...
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... D Q Input Register Address Register OUTPUT REGISTER CLR D Q Binary Counter & Logic [1] BYTE b WRITE D Q BYTE a WRITE D Q ENABLE Input Register Address Register OUTPUT REGISTER D Q CLR Binary Counter & Logic CY7C1361A CY7C1363A DQa,DQb DQc,DQd DQa,DQb Page ...
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... DQb 23 DQa 58 DQb CCQ CCQ CY7C1361A CY7C1363A DQb 80 DQb 79 DQb CCQ DQb DQb 74 DQb 73 72 DQb CCQ 69 DQb DQb 100-pin TQFP ...
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... DQb V CLK DQb V BWE CCQ DQb MODE TMS TDI TCK CCQ CY7C1361A CY7C1363A CCQ DQb DQb SS V DQb DQb SS V DQb V SS CCQ BWb DQb DQb V DQb ...
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... Linear Burst HIGH on this pin selects Interleaved Burst. ZZ Input- Sleep: This active HIGH input puts the device in Asynchronous low-power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). CY7C1361A CY7C1363A Pin Description Page ...
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... Write control and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock’s rising edge. CE Input- Chip Enable: This active LOW input is used to enable the Synchronous device and to gate ADSP. CY7C1361A CY7C1363A Pin Description Pin Description ...
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... Supply Core Power Supply: +3.3V –5% and +10 Ground Ground: GND I/O Power Power Supply for the I/O circuitry CCQ Supply NC – No Connect: These signals are not internally connected. User can leave it floating or connect CY7C1361A CY7C1363A Pin Description Page ...
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... CY7C1361A CY7C1363A Second Third Fourth Address Address Address (internal) (internal) (internal) A...A01 A...A10 A...A11 A...A10 A...A11 A...A00 A...A11 A...A00 A...A01 A...A00 A...A01 A...A10 Write OE CLK ...
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... TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. At power-up, the TAP is reset internally to ensure that TDO High-Z state. CY7C1361A CY7C1363A BWb BWc X X ...
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... TAP controller is in the Capture-DR state, a snap shot of the data in the device’s input and I/O buffers is loaded into the boundary scan register. Because the device system clock(s) are independent from the TAP clock CY7C1361A CY7C1363A Page ...
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... Do not use these instructions. They are reserved for future use. 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram CY7C1361A CY7C1363A SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE- EXIT2-IR 1 UPDATE- [11] Page ...
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... I = 100 A OHC [13 8.0 mA OLT [13 8.0 mA OHT /2; undershoot: V (AC) < – 0.5V for t < t KHKH IL KHKH must not exceed V . Control input signals (such as R/W, ADV/LD) may not have pulse widths less than t CC CY7C1361A CY7C1363A 0 Selection Circuitry [12] Min. Max. 2 0.3 CC –0.3 0.8 – ...
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... Test conditions are specified using the load in TAP AC test conditions. Document #: 38-05259 Rev. *A [16, 17] Over the Operating Range Description THTL t THTH t t MVTH THMX t DVTH t THDX t TLQV t TLQX CY7C1361A CY7C1363A Min. Max ALL INPUT PULSES 3.0V 1.5V 1.5 ns 1.5 ns (b) ...
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... Do not use these instructions; they are reserved for future use. 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations. CY7C1361A CY7C1363A Description Reserved for revision number. Defines depth of 256K or 512K words. Defines width of x36 or x18 bits. ...
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... CY7C1361A CY7C1363A (continued) Signal Name TQFP Bump BWa 93 BWb 94 5G BWc 95 3G BWd 100 2A DQc 1 2D ...
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... CY7C1361A CY7C1363A (continued) Signal Name TQFP Bump ID CLK BWa 93 BWb 100 DQb 8 1D DQb 9 DQb 12 2G DQb 13 1H ...
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... Max. CLK frequency = 0 CC Description Test Conditions T = 25° MHz 3.3V CC pins should be no greater than 200mV. CC < – 2.0V for t < CY7C1361A CY7C1363A [18] Ambient Temperature 3.3V–5/ +10% – Min. 2 2.0 1.7 –0.3 –0.3 – ...
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... V = 3.3V 3.5 CCQ V = 2.5V 4.5 CCQ [15, 21, 26] 0 [15, 21, 26] 3.5 [28] 1.5 [28] 0.5 is less than t and t is less than t KQHZ KQLZ OEHZ CY7C1361A CY7C1363A TQFP Typ ALL INPUT PULSES Vcc 90% 10% GND 1 V/ns (c) 133 MHz 117 MHz 100 MHz Min. Max. Min. Max. Min. 7.5 8.5 10 2.5 3.0 3 ...
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... SINGLE READ , and CE are active CY7C1361A CY7C1363A ...
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... OEHZ D(A1) D(A2) D(A2+2) BURST WRITE CY7C1361A CY7C1363A ...
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... Single Write CY7C1361A CY7C1363A ...
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... Ordering Information Speed (MHz) Ordering Code 150 CY7C1361A-150AJC CY7C1361A-150AC CY7C1361A-150BGC 133 CY7C1361A-133AJC CY7C1361A-133AC CY7C1361A-133BGC 117 CY7C1361A-117AJC CY7C1361A-117AC CY7C1361A-117BGC 100 CY7C1361A-100AJC CY7C1361A-100AC CY7C1361A-100BGC Document #: 38-05259 Rev ZZS I (active Three-state Package Name A101 100-lead 1.4 mm Thin Quad Flat Pack A101 100-lead ...
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... CY7C1363A-150BGC 133 CY7C1363A-133AJC CY7C1363A-133AC CY7C1363A-133BGC 117 CY7C1363A-117AJC CY7C1363A-117AC CY7C1363A-117BGC 100 CY7C1363A-100AJC CY7C1363A-100AC CY7C1363A-100BGC 133 CY7C1361A-133AJI CY7C1361A-133AI CY7C1361A-133BGI 117 CY7C1361A-117AJI CY7C1361A-117AI CY7C1361A-117BGI 100 CY7C1361A-100AJI CY7C1361A-100AI CY7C1361A-100BGI 133 CY7C1363A-133AJI CY7C1363A-133AI CY7C1363A-133BGI 117 CY7C1363A-117AJI CY7C1363A-117AI CY7C1363A-117BGI 100 CY7C1363A-100AJI CY7C1363A-100AI CY7C1363A-100BGI Document #: 38-05259 Rev. *A Package ...
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... Package Diagrams 100-lead Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05259 Rev. *A CY7C1361A CY7C1363A 51-85050-A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-ball BGA ( 2.4) BG119 CY7C1361A CY7C1363A 51-85115-*A ...
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... Document Title:CY7C1361A/CY7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Document Number: 38-05259 REV ECN No. Issue Date ** 113847 05/17/02 *A 116225 06/20/02 Document #: 38-05259 Rev. *A Orig. of Description of Change Change GLC New Data Sheet BRI Removed GVT part numbers from title and body of datasheet Corrected CY part numbers in body of datasheet Corrected the read and write timing diagrams Added note 19 (pg ...