CY7C1339-100AC Cypress Semiconductor Corporation., CY7C1339-100AC Datasheet

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CY7C1339-100AC

Manufacturer Part Number
CY7C1339-100AC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1339-100AC
Manufacturer:
CYPRESS
Quantity:
142
Part Number:
CY7C1339-100AC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Features
Functional Description
The CY7C1339 is a 3.3V, 128K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Intel and Pentium are trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Logic Block Diagram
Cypress Semiconductor Corporation
• Supports 100-MHz bus for Pentium
• Fully registered inputs and outputs for pipelined oper-
• 128K by 32 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
• User-selectable burst counter supporting Intel
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
operations with zero wait states
ation
tium interleaved or linear burst sequences
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
ADSP
ADSC
A
BW
BWE
CE
CE
CE
ADV
GW
CLK
[16:0]
BW
BW
BW
OE
ZZ
0
1
2
3
2
1
3
17
128K x 32 Synchronous-Pipelined Cache RAM
(A
MODE
[1;0]
and PowerPC™
)
2
15
3901 North First Street
CE
CE
CLR
D
D
D
D
D
D
CE
D
ENABLE DELAY
CLK
CLK
BYTEWRITE
REGISTERS
BYTEWRITE
REGISTERS
BYTEWRITE
REGISTERS
REGISTERS
BYTEWRITE
DQ[23:16]
REGISTER
DQ[31:24]
REGISTER
COUNTER
REGISTER
DQ[15:8]
CONTROL
ADDRESS
DQ[7:0]
ENABLE
SLEEP
BURST
Pen-
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
1
15
The CY7C1339 I/O pins can operate at either the 2.5V or the
3.3V level; the I/O pins are 3.3V tolerant when V
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1339 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can
be initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
[3:0]
San Jose
) inputs. A Global Write Enable (GW) overrides
17
CLK
REGISTERS
OUTPUT
CA 95134
32
MEMORY
128KX32
ARRAY
1
, CE
CY7C1339
CLK
2
REGISTERS
, CE
August 2, 1999
INPUT
408-943-2600
DDQ
32
3
DQ
) and an
=2.5V.
[31:0]

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CY7C1339-100AC Summary of contents

Page 1

... ZZ Intel and Pentium are trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. Cypress Semiconductor Corporation The CY7C1339 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when V and PowerPC™ All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock ...

Page 2

... TQFP 15 CY7C1339 7C1339-166 3.5 Commercial 420 Commercial 10 2 CY7C1339 DDQ V 76 SSQ BYTE1 SSQ V 70 DDQ 69 DQ ...

Page 3

... Selects burst order. When tied to GND selects linear burst sequence. When tied left floating selects interleaved burst sequence. This is a strap pin and DDQ should remain static during device operation. No Connects. 3 CY7C1339 , CE , and are also loaded into the ...

Page 4

... Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1339 is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data is to the DQ ...

Page 5

... ADSP, and ADSC must remain inactive for the duration of t ZZREC 01 10 Test Conditions Min ZZ > > < 0.2V 2t CYC 5 CY7C1339 after the ZZ input returns LOW. Max Unit CYC ns ...

Page 6

... CY7C1339 ADV OE DQ Write Hi-Z Read Hi-Z ...

Page 7

... Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 +150 C Operating Range +125 C 0.5V to +4.6V Range Temperature Com’ + 0. CY7C1339 ...

Page 8

... DDQ 7.5 ns cycle, 133 MHz 1/t MAX CYC 10 ns cycle, 100 MHz Max Device Deselected Test Conditions MHz 3.3V 3.3V DDQ 8 CY7C1339 Min. Max. Unit 3.135 3.6 V 2.375 3.6 V 2.4 V 0.4 V 2 0.3 0 ...

Page 9

... EOHZ R=317 3.3V OUTPUT 2. GND R=351 INCLUDING JIG AND SCOPE (b) [11,12,13] -166 Min. Max. 6.0 1.7 1.7 2.0 0.5 3.5 1.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 3.5 0 [12, 13] 3.5 [12, 13] 0 [12] 3.5 is less than t and t is less than t . EOLZ CHZ CLZ 9 CY7C1339 [10] ALL INPUT PULSES 90% 90% 10% 10% 2.5ns 2.5 ns (c) -133 -100 Min. Max. Min. Max. Unit 7.5 10 1.9 3.5 1.9 3.5 2.5 2.5 0.5 0.5 4.0 5.5 2.0 2.0 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2.5 0.5 0.5 2.5 2.5 ...

Page 10

... GW to define a write cycle (see Write Cycle Descriptions table). [3:0] 15. WDx stands for Write Data to Address X. B urst W rite ADSP ignored with CE inactive masks ADSP UNDEFINED = DON’T CARE 10 CY7C1339 Pipelined Write Unselected ADSC initiated write WD3 Unselected with CE 2 High-Z 3a ...

Page 11

... RDx stands for Read Data from Address X. Burst Read ADSP ignored with Suspend Burst ADH masks ADSP OEHZ t DOH CLZ = DON’T CARE = UNDEFINED 11 CY7C1339 Unselected Pipelined Read inactive 1 ADSC initiated read RD3 Unselected with CHZ ...

Page 12

... Single Write Burst Read CH t ADSP ignored with ADH RD3 masks ADSP 1 t OEHZ t DS See Note Out Out In = DON’T CARE = UNDEFINED 12 CY7C1339 Unselected Pipelined Read inactive DOH Out Out Out t CHZ ...

Page 13

... OE t CLZ Data In/Out 1a 2a Out Out t CO Back to Back Reads CYC CH CL WD1 t ADH t CEH t WES ADSP ignored with CE HIGH Out Out In t DOH = DON’T CARE = UNDEFINED 13 CY7C1339 WD2 WD3 WD4 t WEH D( CHZ ...

Page 14

... ADSC CE 1 LOW CE 2 HIGH I/O’s NotefjdfdhfdjfdfjdjdjdjNo Note: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. I/Os are in three-state when exiting ZZ sleep mode. t ZZS I (active DDZZ Three-state 14 CY7C1339 t ZZREC ...

Page 15

... CY7C1339-166AC 133 CY7C1339-133AC 100 CY7C1339-100AC Document #: 38-00723-B Package Diagram 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

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