CY28349BOC Cypress Semiconductor Corporation., CY28349BOC Datasheet
CY28349BOC
Related parts for CY28349BOC
CY28349BOC Summary of contents
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Features ® • Compatible to Intel CK-Titan and CK-408 Clock Synthesizer/driver specifications • System frequency synthesizer for Intel Brookdale 845 ® and Brookdale – G Pentium 4 chipsets • Programmable clock output frequency with less than 1-MHz increment • Integrated ...
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Pin Definitions Pin Pin Name Pin No. Type REF0/MULTSEL0 48 REF1/MULTSEL1 1 CPU0:1, CPU0:1# 41, 38, 40, 37 CPU_ITP, 44, 45 CPU_ITP# 3V66_0:2 31, 30, 28 PCI_F0/FS2 6 PCI_F1/FS3 7 PCI_F2 8 PCI0/FS4 10 PCI1:6 11, ...
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Pin Definitions (continued) Pin Pin Name Pin No. Type PWR_DWN# 42 SCLK 26 SDATA 25 RST# 20 (open-d rain) IREF 35 VTT_PWRGD# 19 VDD_REF 18, 24, VDD _PCI, 32, 39, 46 VDD_48MHz, VDD_3V66, VDD_CPU GND_PCI, 5, 13, 21, ...
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Swing Select Functions Board Target MULTSEL1 MULTSEL0 Trace/Term 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 0 ...
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Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can be individually enabled or disabled. ...
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Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Description 9 Write 10 Acknowledge from slave 11:18 Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of ...
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Data Byte 2 Bit Pin# Name Bit 7 – Reserved Bit 6 17 PCI6 Bit 5 16 PCI5 Bit 4 15 PCI4 Bit 3 14 PCI3 Bit 2 12 PCI2 Bit 1 11 PCI1 Bit 0 10 PCI0 Data Byte ...
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Data Byte 5 (continued) Bit Pin# Name Bit 2 – FS_Override Bit 1 27 SEL 3V66 Bit 0 23 SEL 48MHZ Data Byte 6 Bit Pin# Name Bit 7 – Revision_ID3 Bit 6 – Revision_ID2 Bit 5 – Revision_ID1 Bit ...
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Data Byte 9 Bit Pin# Name Bit 7 – 48MHz_DRV Bit 6 – PCI_DRV Bit 5 – 3V66_DRV Bit 4 – RST_EN_WD Bit 3 – RST_EN_FC Bit 2 – WD_TO_STATUS Bit 1 – WD_EN Bit 0 – Reserved Data Byte ...
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Data Byte 10 (continued) Bit Pin# Name Bit 3 – PCI_Skew1 Bit 2 – PCI_Skew0 Bit 1 – 3V66_Skew1 Bit 0 – 3V66_Skew0 Data Byte 11 Bit Pin# Name Bit 7 – ROCV_FREQ_N7 Bit 6 – ROCV_FREQ_N6 Bit 5 – ...
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Data Byte 13 Bit Pin# Name Bit 7 – CPU_FSEL_N7 Bit 6 – CPU_FSEL_N6 Bit 5 – CPU_FSEL_N5 Bit 4 – CPU_FSEL_N4 Bit 3 – CPU_FSEL_N3 Bit 2 – CPU_FSEL_N2 Bit 1 – CPU_FSEL_N1 Bit 0 – CPU_FSEL_N0 Data Byte ...
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Data Byte 17 Bit Pin# Name Bit 7 – Reserved Bit 6 – Reserved Bit 5 – Reserved Bit 4 – Reserved Bit 3 – Reserved Bit 2 – Reserved Bit 1 – Reserved Bit 0 – Reserved Table 4. ...
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Table 4. Frequency Selection Table (continued) Input Conditions FS4 FS3 FS2 FS1 SEL4 SEL3 SEL2 SEL1 Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate ...
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Table 5. Register Summary (continued) Name WD_TO_STATUS Watchdog Timer Time-out Status bit time-out occurs (READ); Ignore (WRITE Time-out occurred (READ); Clear WD_TO_STATUS (WRITE). WD_TIMER[4:0] These bits store the time-out value of the Watchdog timer. The ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage ..................................................–0.5 to +7.0V Input Voltage .............................................. –0. Operating Conditions Over which Electrical Parameters are Guaranteed Parameter ...
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Switching Characteristics Over the Operating Range Parameter Output t All Output Duty Cycle 1 t CPU Rise Time 2 t 48MHz, REF Rising Edge Rate 2 t PCI, 3V66, Rising Edge Rate 2 t CPU Fall Time 3 t ...
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Switching Waveforms Duty Cycle Timing (Single-ended Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock Skew ...
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... CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK Ordering Information Ordering Code CY28349BOC 48-pin SSOP CY28349BOCT 48-pin SSOP – Tape and Reel Lead-free CY28349BOXC 48-pin SSOP CY28349BOXCT 48-pin SSOP – Tape and Reel Document #: 38-07454 Rev ...
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Layout Example +3.3V Supply FB 0.005µ VDDQ3 5Ω Dale ILB1206 - 300 (300Ω @ 100 MHz) Ceramic Caps C3 = 10–22 µ VIA to GND plane layer Note: ...
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Package Diagram 48-lead Shrunk Small Outline Package O48 Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07454 Rev. *B © ...
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Document History Page Document Title: CY28349B FTG for Intel Document Number: 38-07454 Issue Orig. of REV. ECN NO. Date Change ** 117127 08/13/02 *A 122932 12/17/02 *B 334154 See ECN Document #: 38-07454 Rev. *B ® ® Pentium 4 CPU ...