CY28347ZC Cypress Semiconductor Corporation., CY28347ZC Datasheet
CY28347ZC
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CY28347ZC Summary of contents
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Features • Supports VIA P4M266/KM266 chipsets ® • Supports Pentium 4, Athlon processors • Supports two DDR DIMMS • Provides — Two different programmable CPU clock pairs — Six differential DDR SDRAM pairs — Two low-skew/low-jitter AGP clocks — Six ...
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Pin Description Pin Name PWR 3 XIN 4 XOUT VDD 1 FS0/REF0 VDD 56 VTTPWRGD# VDDR REF1 VDDR 44,42,38, DDRT(0:5) VDDD 36,32,30 43,41,37 DDRC(0:5) VDDD 35,31,29 7 SELP4_K7#/ VDDAGP I/O AGP1 12 MULTSEL/PCI2 VDDPCI 53 CPUT/CPUOD_T VDDC 52 CPUC/CPUOD_C ...
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Pin Description (continued) Pin Name PWR 6 MODE/AGP0 VDDAGP I/O 8 PCI_STP# VDDAGP 25 IREF 28 SDATA 27 SCLK 26 PD# 45 BUF_IN 46 FBOUT 5 VDDAGP 51 VDDC 16 VDDPCI 55 VDDR 50 VDDI 22 VDD48M 23 VDD ...
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Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. ...
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Table 6. Byte Read and Byte Write Protocol (continued) 10 Acknowledge from slave 11:18 Command Code - 8 bits “1xxxxxxx” stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 Acknowledge ...
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Byte 2: PCI Clock Register (continued) Bit @Pup Pin Byte 3: AGP/Peripheral Clocks Register Bit @Pup Pin ...
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Table 8. Dial-A-Ratio™ AGP(0:2) DARAG (1: Byte 5: DDR Clock Register Bit @Pup Pin BUF_IN threshold voltage DDR Mode, BUF_IN threshold setting 1.15V 1.05V ...
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Byte 8: Silicon Signature Register (all bits are Read-only) Bit @Pup Name 7 0 Revision_ID3 6 0 Revision_ID2 5 0 Revision_ID1 4 0 Revision_ID0 3 1 Vender_ID3 2 0 Vender_ID2 1 0 Vender_ID1 0 0 Vender_ID0 Byte9: Dial-A-Frequency Control Register ...
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Maximum Ratings Input Voltage Relative to V :.............................. V SS Input Voltage Relative DDQ Storage Temperature: ................................– 150 C Operating Temperature: .................................... +70 C Maximum ESD .............................................................2000V Maximum Power ...
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AC Parameters (continued) Parameter Description P4 Mode CPU at 0.7V TDC CPUT/C Duty Cycle TPeriod CPUT/C Period Tr/Tf CPUT/C Rise and Fall Times Rise/Fall Matching Delta Tr/Tf Rise/Fall Time Variation TSKEW CPUT/C to CPUCS_T/C Clock Skew TCCJ CPUT/C Cycle-to-Cycle Jitter ...
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AC Parameters (continued) Parameter Description CPUCS_T/C Rise and Fall Times VD Differential Voltage AC VX Differential Crossover Voltage AGP TDC AGP(0:2) Duty Cycle TPeriod AGP(0:2) Period THIGH AGP(0:2) HIGH Time TLOW AGP(0:2) LOW Time Tr/Tf AGP(0:2) Rise ...
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AC Parameters (continued) Parameter Description REF TDC REF Duty Cycle TPeriod REF Period Tr/Tf REF Rise and Fall Times TCCJ REF Cycle-to-Cycle Jitter DDR VX Crossing Point Voltage of DDRT/C VD Differential Voltage Swing TDC DDRT/C(0:5) Duty Cycle TPeriod DDRT/C(0:5) ...
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For Open Drain CPU Output Signals (with K7 Processor SELP4_K7 Ohm CPUOD_T 47 Ohm CPUOD_C For Differential CPU Output Signals (with P4 Processor SELP4_K7#= 1) The following diagram shows lumped test load configurations for the differential Host ...
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CPUT MULTSEL 33 CPUC IREF 475 Table 10. Group Timing Relationships and Tolerances t CPUCS to AGP CSAGP t AGP to PCI AP Table 11. Signal Loading REF (0:1), 48MHz (USB), 24_48MHz AGP(0:2), PCI_F(0:5)SDRAM (0:11) FBOUT DDRT/C CPUT/C CPUOD_T/C ...
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CPU_STP# Assertion (P4 Mode) When CPU_STP# pin is asserted, all CPU outputs will be stopped after being sampled by two rising CPUC clock edges. The final state of the stopped CPU signal is CPUT = HIGH and CPUC = LOW. ...
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CPU_STP# Assertion (K7 Mode) When CPU_STP# pin is asserted, all CPU outputs will be stopped after being sampled by two rising CPUC clock edges. CPU_STP# CPUOD_T CPUOD_C Figure 9. CPU_STP# Assertion Waveform (K7 Mode) CPU_STP# Deassertion (K7 Mode) The deassertion ...
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PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The setup PCI_STP# PCI_F PCI(1:6) PCI_STP#- Deassertion The deassertion of the ...
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P4 Processor SELP4_K7 RDW N# CPUT 133MHz CPUC 133MHz PCI 33MHz AGP 66MHz USB 48MHz REF 14.318MHz DDRT 133MHz DDRC 133MHz Figure 13. Power-down Assertion Timing Waveform (in P4 Mode) Power-down Deassertion (P4 Mode) The power-up latency ...
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AMD K7 processor SELP4_K7 Power-down Assertion (K7 Mode) When the PD# signal is asserted LOW, all clocks are disabled to a LOW level in an orderly fashion prior to removing power from the CPU. When PD# is sampled ...
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... Shrunk Small Outline Package (SSOP) – Tape and Reel CY28347ZC 56-pin Thin Shrunk Small Outline package (TSSOP) CY28347ZCT 56-pin Thin Shrunk Small Outline package (TSSOP) – Tape and Reel Note: 26. This timing diagram shows that VTT_PWRGD# transits to a logic LOW in the first time at power up. After the first HIGH to LOW transition of VTT_PWRGD#, device is not affected, VTT_PWRGD# is ignored ...
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Package Drawing and Dimensions 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights ...
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Document Title: CY28347 Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems Document Number: 38-07352 Issue REV. ECN NO. Date ** 112259 03/29/02 *A 120421 10/23/02 *B 121771 12/06/02 *C 122902 12/26/02 Document #: 38-07352 Rev. *C Orig. of Change ...