CY28323BPVC Cypress Semiconductor Corporation., CY28323BPVC Datasheet
CY28323BPVC
Available stocks
Related parts for CY28323BPVC
CY28323BPVC Summary of contents
Page 1
FTG for Intel Features • Compatible to Intel ® CK-Titan & CK-408 Clock Synthe- sizer/Driver Specifications • System frequency synthesizer for Intel Brookdale 845 and Brookdale - G Pentium 4 Chipsets ® • Programmable clock output frequency with less than ...
Page 2
Pin Definitions Pin Pin Name Pin No. Type REF0/MULTSEL0 48 I/O REF1/MULTSEL1 1 I/O CPU0:1, CPU0:1# 41, 38, 40, 37 CPU_ITP, 44, 45 I/O CPU_ITP# 3V66_0:3 31, 30, 28, 27 PCI_F0/FS2 6 I/O PCI_F1/FS3 7 I/O ...
Page 3
Pin Definitions (continued) Pin Pin Name Pin No. Type 24_48MHz/FS1 23 I/O PWR_DWN# 42 SCLK 26 SDATA 25 I/O RST# 20 (open- drain) IREF 35 VTT_PWRGD# 19 VDD_REF 18, 24, 32, 39, 46 VDD _PCI, VDD_48MHz, VDD_3V66, VDD_CPU ...
Page 4
Swing Select Functions Board Target MULTSEL1 MULTSEL0 Trace/Term 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 50Ω 60Ω 0 ...
Page 5
Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can be individually enabled or dis- ...
Page 6
Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 Write 10 Acknowledge from slave 11:18 Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of ...
Page 7
Data Byte 1 (continued) Bit Pin# Name Bit 2 28 3V66_2 Bit 1 30 3V66_1 Bit 0 31 3V66_0 Data Byte 2 Bit Pin# Name Bit 7 -- Reserved Bit 6 17 PCI6 Bit 5 16 PCI5 Bit 4 15 ...
Page 8
Data Byte 5 Bit Pin# Name Bit 7 10 Latched FS4 input Bit 6 7 Latched FS3 input Bit 5 6 Latched FS2 input Bit 4 23 Latched FS1 input Bit 3 22 Latched FS0 input Bit 2 -- FS_Override ...
Page 9
Data Byte 8 Bit Pin# Name Bit 7 -- Reserved Bit 6 -- Reserved Bit 5 -- WD_TIMER4 Bit 4 -- WD_TIMER3 Bit 3 -- WD_TIMER2 Bit 2 -- WD_TIMER1 Bit 1 -- WD_TIMER0 Bit 0 -- WD_PRE_SCALER Data Byte ...
Page 10
Data Byte 10 Bit Pin# Name Bit 7 -- CPU_Skew2 Bit 6 -- CPU_Skew1 Bit 5 -- CPU_Skew0 Bit 4 -- Reserved Bit 3 -- PCI_Skew1 Bit 2 -- PCI_Skew0 Bit 1 -- 3V66_Skew1 Bit 0 -- 3V66_Skew0 Data Byte ...
Page 11
Data Byte 12 (continued) Bit Pin# Name Bit 6 -- ROCV_FREQ_M6 Bit 5 -- ROCV_FREQ_M5 Bit 4 -- ROCV_FREQ_M4 Bit 3 -- ROCV_FREQ_M3 Bit 2 -- ROCV_FREQ_M2 Bit 1 -- ROCV_FREQ_M1 Bit 0 -- ROCV_FREQ_M0 Data Byte 13 Bit Pin# ...
Page 12
Data Byte 15 (continued) Bit Pin# Name Bit 1 -- Vendor Test Mode Bit 0 -- Vendor Test Mode Data Byte 16 Bit Pin# Name Bit 7 -- Reserved Bit 6 -- Reserved Bit 5 -- Reserved Bit 4 -- ...
Page 13
Table 4. Frequency Selection Table Input Conditions FS4 FS3 FS2 FS1 SEL4 SEL3 SEL2 SEL1 ...
Page 14
Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency in the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the ...
Page 15
Table 5. Register Summary (continued) Name WD_TO_STATUS Watchdog Timer Time-out Status bit time-out occurs (READ); Ignore (WRITE Time-out occurred (READ); Clear WD_TO_STATUS (WRITE) WD_TIMER[4:0] These bits store the time-out value of the Watchdog timer. The ...
Page 16
Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage ................................................. –0.5 to +7.0V Input Voltage ............................................ –0. Operating Conditions Over which Electrical Parameters are Guaranteed Parameter ...
Page 17
Switching Characteristics Over the Operating Range Parameter Output Description t All Output Duty Cycle 1 t CPU Rise Time 2 t 48MHz, REF Rising Edge Rate 2 t PCI, 3V66, Rising Edge Rate 2 t CPU Fall Time ...
Page 18
Switching Waveforms Duty Cycle Timing (Single Ended Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock ...
Page 19
... CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK Ordering Information Ordering Code CY28323BPVC 48-pin Small Shrunk Outline Package (SSOP) CY28323BPVCT 48-pin Small Shrunk Outline Package (SSOP)- Tape and Reel Document #: 38-07453 Rev Package Type ...
Page 20
Layout Example +3.3V Supply FB 0.005 µ VDDQ3 5Ω Dale ILB1206 - 300 (300Ω @ 100 MHz) Ceramic Caps C3 = 10–22 µ VIA to GND plane layer ...
Page 21
Package Diagram 48-Lead Shrunk Small Outline Package O48 Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07453 Rev. *B © ...
Page 22
Document Title: CY28323B FTG For Intel Document Number: 38-07453 Issue Orig. of REV. ECN NO. Date Change ** 117126 08/19/02 *A 122931 12/17/02 *B 131345 11/20/03 Document #: 38-07453 Rev. *B ® ® Pentium 4 CPU and Chipsets Description of ...