CY2310ANZPVC-1T Cypress Semiconductor Corporation., CY2310ANZPVC-1T Datasheet

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CY2310ANZPVC-1T

Manufacturer Part Number
CY2310ANZPVC-1T
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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1CY2310NZCY2310
NZCY2310ANZ
Cypress Semiconductor Corporation
Document #: 38-07142 Rev. *B
Features
• One input to 10 output buffer/driver
• Supports up to four SDRAM SO-DIMMs
• Two additional outputs for feedback
• Serial interface for output control
• Low skew outputs
• Up to 100-MHz operation
• Multiple V
• Dedicated OE pin for testing
• Space-saving 28-pin SSOP package
• 3.3V operation
Block Diagram
SCLOCK
BUF_IN
SDATA
OE
DD
and V
SS
pins for noise reduction
Serial Interface
Decoding
3901 North First Street
3.3V SDRAM Buffer for Mobile PCs
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
Functional Description
The CY2310ANZ is a 3.3V buffer designed to distribute
high-speed clocks in mobile PC applications. The part has 10
outputs, 8 of which can be used to drive up to four SDRAM
SO-DIMMs, and the remaining can be used for external
feedback to a PLL. The device operates at 3.3V and outputs
can run up to 100 MHz, thus making it compatible with
Pentium II
conjunction with the CY2281 or similar clock synthesizer for a
full Pentium II motherboard solution.
The CY2310ANZ also includes a serial interface which can
enable or disable each output clock. On power-up, all output
clocks are enabled. A separate Output Enable pin facilitates
testing on ATE.
®
processors. The CY2310ANZ can be used in
San Jose
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM8
BUF_IN
SDATA
V
DDIIC
V
V
V
V
V
V
Pin Configuration
,
DD
DD
DD
SS
SS
SS
CA 95134
with 4 SO-DIMMs
28-pin SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
Revised January 19, 2005
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CY2310ANZ
408-943-2600
V
SDRAM7
SDRAM6
V
V
SDRAM5
SDRAM4
V
OE
V
SDRAM9
V
V
SCLOCK
DD
SS
DD
SS
DD
SS
SSIIC
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CY2310ANZPVC-1T Summary of contents

Page 1

NZCY2310ANZ Features • One input to 10 output buffer/driver • Supports up to four SDRAM SO-DIMMs • Two additional outputs for feedback • Serial interface for output control • Low skew outputs • 100-MHz operation • Multiple ...

Page 2

Pin Summary Name Pins 10, 19, 24 12, 17, 21 DDIIC V 16 SSIIC BUF_IN SDATA 14 SCLK 15 SDRAM [0– ...

Page 3

Maximum Ratings Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage (Except BUF_IN)........–0. Input Voltage (BUF_IN)............................ –0.5V to +7.0V Operating Conditions Parameter V Supply Voltage DD T Operating Temperature (Ambient Temperature Load ...

Page 4

Switching Characteristics [3] Parameter Name Maximum Operating Frequency [2, 4] ÷ t Duty Cycle = [2] t Rising Edge Rate 3 [2] t Falling Edge Rate 4 [2] t Output to Output Skew 5 t SDRAM Buffer ...

Page 5

Switching Waveforms (continued) SDRAM Buffer LH and HL Propagation Delay INPUT OUTPUT t 6 SDRAM Buffer Enable and Disable Times OE Three-State Active OUTPUTS t 8 Test Circuit 0.1 µF Document #: 38-07142 Rev ...

Page 6

Application Information Clock traces must be terminated with either series or parallel termination normally done. Summary • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF. In some ...

Page 7

... Ordering Information Ordering Code Standard CY2310ANZPVC–1 CY2310ANZPVC–1T Lead-free CY2310ANZPVXC–1 CY2310ANZPVXC–1T Package Diagram 28-Lead (5.3 mm) Shrunk Small Outline Package O28 Pentium registered trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. ...

Page 8

Document History Page Document Title: CY2310ANZ 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs Document Number: 38-07142 Issue Orig. of REV. ECN NO. Date Change ** 110251 11/18/01 *A 121829 12/14/02 *B 310555 See ECN Document #: 38-07142 Rev. ...

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