CY7C1367B-166AI Cypress Semiconductor Corporation., CY7C1367B-166AI Datasheet
CY7C1367B-166AI
Related parts for CY7C1367B-166AI
CY7C1367B-166AI Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-05096 Rev. *B Functional Description The CY7C1366B/CY7C1367B SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The ...
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... BYTE BW B WRITE REGISTER DQ DQP BYTE A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL 2 Logic Block Diagram – CY7C1367B (512K x 18) ADDRESS A0, A1, A REGISTER MODE ADV CLK ADSC ADSP DQ DQP B, B BYTE BW B WRITE REGISTER DQ DQP BYTE BW A WRITE REGISTER BWE GW ...
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... TQFP Pinout (3 Chip Enables) DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP CY7C1366B CY7C1367B DDQ V 76 SSQ NC 75 DQP SSQ V 70 DDQ CY7C1367B (512K x 18 DDQ V 60 SSQ SSQ V 54 DDQ Page ...
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... Document #: 38-05096 Rev. *B 119-ball BGA (2 Chip Enable with JTAG) CY7C1366B (256K x 36 ADSP CE A ADSC DQP ADV CLK BWE DQP MODE TMS TDI TCK CY7C1367B (512K x 18 ADSP CE A ADSC ADV CLK BWE DQP MODE TMS TDI TCK CY7C1366B CY7C1367B DDQ A A ...
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... V B DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05096 Rev. *B 165-ball fBGA (3 Chip Enable) CY7C1366B (256K x 36 CLK 18M SS TDI TMS CY7C1367B (512K x 18 CLK ‘ 18M SS TDI TMS CY7C1366B CY7C1367B ADSC ADV BWE ADSP DDQ DDQ DDQ ...
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... CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. CY7C1366B CY7C1367B Description [2] are sampled active. A1: A0 are fed to the 3 and BWE). ...
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... Serial data-In to the JTAG circuit. Sampled on the input rising edge of TCK. If the JTAG feature is not being Synchronous utilized, this pin can be disconnected or connected CY7C1366B CY7C1367B Description are placed in a three-state X or left floating selects DD . This pin is not available on TQFP packages. . This pin is not available on TQFP packages. ...
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... CY7C1366B–Pin Definitions BGA (2 Chip Name TQFP Enable) TCK – 14,16,66, B1,C1,R1, 42,39,38 T1,T2,J3, D4,L4,5J, 5R,6T,6U, B7,C7,R7 CY7C1367B–Pin Definitions BGA (2-Chip Name TQFP Enable 37,36,32,33, P4,N4,A2 34,35,43,44, C2,R2,T2, 45,46,47,48, A3,B3,C3, 49,50,80,81, T3,A5,B5, 82,99,100 C5,T5,A6, B6,C6,R6, T6 93,94 G3, BWE CLK 89 K4 ...
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... CY7C1367B–Pin Definitions BGA (2-Chip Name TQFP Enable ADV 84 A4 ADSP P4 85 ADSC DQs, DQPs 58,59,62,63, P7,K7,G7, 68,69,72,73, E7,F6,H6, 8,9,12,13,18 L6,N6,D1, ,19,22,23,74 H1,L1,N1, ,24 E2,G2,K2, M2,D6,P2 V 15,41,65,91 C4,J2,J4, DD J6,R4 V 17,40,67,90 D3,D5,E5, SS E3,F3,F5, G5,H3,H5, K3,K5,L3, M3,M5,N3, N5,P3,P5 V 5,10,21,26, – SSQ 55,60,71,76 Document #: 38-05096 Rev. *B ...
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... CY7C1367B–Pin Definitions BGA (2-Chip Name TQFP Enable) V 4,11,20,27, A1,A7,F1, DDQ 54,61,70,77 F7,J1,J7, M1,M7,U1, U7 MODE 31 R3 TDO – U5 TDI – U3 TMS – U2 TCK – 1,2,3,6,7,14, B1,B7,C1, 16,25,28,29, C7,D2,D4, 30,38,39,42, D7,E1,E6, 51,52,53,56, H2,F2,G1, 57,66,75,78, G6,H7,J3, 79,95,96 J5,K1,K6, L4,L2,L7, M6,N2,L7, P1,P6,R1, R5,R7,T1, T4,U6 Document #: 38-05096 Rev ...
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... Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1366B/CY7C1367B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ three-state the output drivers safety precaution, DQ automatically three-stated whenever a write cycle is detected, regardless of the state of OE ...
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... valid Appropriate write will be done based on which byte write is active. X CY7C1366B CY7C1367B Second Third Fourth Address Address Address A1: A0 A1 after the ZZ input returns ZZREC Min. Max CYC 2t CYC 2t CYC 0 ADSC ADV WRITE OE CLK L-H three-state L-H three-state L-H three-state L-H three-state ...
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... D D Write Bytes D, A Write Bytes D, B Write Bytes Write Bytes D, C Write Bytes Write Bytes Write All Bytes Write All Bytes [5] Truth Table for Read/Write Function (CY7C1367B) Read Read Write Byte A – and DQP ) A A Write Byte B – and DQP ) B ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1366B/CY7C1367B incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TAP controller’s capture setup plus t t hold time ( CS plus CH). The SRAM clock input might not be captured correctly if there portion way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1366B CY7C1367B Unlike the SAMPLE/PRELOAD Page ...
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... TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1366B CY7C1367B Page ...
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... CH refer to the setup and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test Conditions. t Document #: 38-05096 Rev CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE [10, 11] Over the operating Range /t = 1ns CY7C1366B CY7C1367B TDOV t TDOX UNDEFINED Symbol Min Max t 50 TCYC ...
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... Reserved for Internal Use 000000 000000 Defines memory type and architecture 100110 010110 Defines width and density 00000110100 00000110100 Allows unique identification of SRAM vendor Indicates the presence register. CY7C1366B CY7C1367B ........................................ V SS 1.25V 20pF O (0°C < TA < +70° 3.3V ±0.165V unless DD Min. Max. 2.4 2 ...
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... Internal Internal Internal Internal CY7C1366B CY7C1367B CY7C1367B (512K x 18) Signal Signal Name BIT# BALL ID Name CLK BWE ADSC 41 T3 ADSP 42 R2 ADV 43 R3 MODE A 44 Internal Internal A 45 Internal Internal A 46 Internal Internal Internal 47 Internal Internal Internal 48 P2 DQP Internal 49 N1 ...
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... Internal Internal A Internal 60 Internal Internal 61 Internal Internal 62 Internal Internal 63 C2 Internal Internal A 68 Internal Internal A CY7C1367B (512K x 18) Signal Name BIT# BALL ID B6 CLK BWE ADSC ADSP ADV Internal A 45 Internal A 46 Internal Internal 47 Internal Internal 48 N1 Internal 49 M1 DQP 50 L1 ...
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... DQ 20 J10 K10 L10 M10 Internal Internal C C1 DQP 26 Internal Internal Internal R11 R10 P10 P11 CY7C1366B CY7C1367B CY7C1367B (512K x 18) Signal Name BIT# BALL Internal Internal A Internal 60 Internal Internal 61 Internal Internal 62 Internal Internal 63 B2 Internal Internal Internal Page Signal Name ...
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... /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < CY7C1366B CY7C1367B Ambient Temperature V DD 0°C to +70°C 3.3V– 5%/+10% 2.5V – 5% -40°C to +85°C Min. Max. 3.135 3.6 3.135 V DD 2.375 2.625 2.4 2 ...
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... Test Conditions Package T = 25qC MHz 3.3V 2.5V DDQ R = 317: 3.3V OUTPUT 351: INCLUDING JIG AND (b) SCOPE R = 1667: 2.5V OUTPUT =1538: INCLUDING JIG AND (b) SCOPE CY7C1366B CY7C1367B TQFP BGA fBGA Package Package Package TQFP BGA fBGA Package Package ALL INPUT PULSES V DD ...
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... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1366B CY7C1367B 200 MHz 166 MHz Min. Max Min. Max 1 1 5.0 6.0 2.0 2 ...
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... ADV suspends burst t OEV OELZ t OEHZ t DOH Q(A2) Q( Q(A1) DON’T CARE is HIGH and CE is LOW. When CE is HIGH CY7C1366B CY7C1367B A3 Burst continued with new base address Deselect cycle Q( Q( Q(A2) Q( Burst wraps around to its initial state BURST READ UNDEFINED is HIGH LOW HIGH ...
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... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05096 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1366B CY7C1367B ADSC extends burst t ADS t ADH A3 t WES t WEH t ADVS t ADVH D( D(A3 Extended BURST WRITE Page ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC . 25 HIGH. Document #: 38-05096 Rev WES t WEH OELZ D(A3) t OEHZ Q(A2) Q(A4) Single WRITE UNDEFINED DON’T CARE CY7C1366B CY7C1367B A5 D(A5) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs Page D(A6) ...
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... CY7C1366B-200AC CY7C1367B-200AC CY7C1366B-200AI CY7C1367B-200AI CY7C1366B-200BGC CY7C1367B-200BGC CY7C1366B-200BGI CY7C1367B-200BGI CY7C1366B-200BZC CY7C1367B-200BZC CY7C1366B-200BZI CY7C1367B-200BZI Notes: 26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 27. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05096 Rev. *B ...
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... Ordering Information (continued) Speed (MHz) Ordering Code 166 CY7C1366B-166AC CY7C1367B-166AC CY7C1366B-166AI CY7C1367B-166AI CY7C1366B-166BGC CY7C1367B-166BGC CY7C1366B-166BG ICY7C1367B-166BGI CY7C1366B-166BZC CY7C1367B-166BGC CY7C1366B-166BZI CY7C1367B-166BGI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 ...
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... Package Diagrams (continued) Document #: 38-05096 Rev. *B 119-Lead PBGA ( 2.4 mm) BG119 CY7C1366B CY7C1367B 51-85115-*B Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1366B CY7C1367B 51-85122-*C Page ...
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... Document History Page Document Title: CY7C1366B/CY7C1367B 9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM Document Number: 38-05096 REV. ECN NO. Issue Date ** 117903 08/28/02 *A 121066 11/13/02 *B 206401 See ECN Document #: 38-05096 Rev. *B Orig. of Change Description of Change RCS New Data Sheet DSG Updated package drawings 51-85115 (BG 119 and 51-85122 (BB165A ...