CY7C1302V25-100BZC Cypress Semiconductor Corporation., CY7C1302V25-100BZC Datasheet
CY7C1302V25-100BZC
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CY7C1302V25-100BZC Summary of contents
Page 1
... I/O devices. Accesses to the CY7C1302V25 Read and Write ports are completely inde- pendent of one another. All accesses are initiated synchro- nously on the rising edge of the positive input clock (K). In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces ...
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... VDD VSS VDD VDDQ VDD VSS VDD VDDQ VDD VSS VDD VDDQ VDD VSS VDD VDDQ VSS VSS VDD VDDQ VSS VSS VSS VSS VSS VSS VSS VSS CY7C1302V25 RPS NC/ Gnd/ NC 18M 72M VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VREF ZQ ...
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... When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. The CY7C1302V25 is organized internally as 256Kx36. Each read access consists of a burst of two sequential 18-bit transfers. Positive Output Clock Input used in conjunction with C to clock out the Read data from the device ...
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... Address expansion for 36M. This is not connected to the die. Address expansion for 72M. This should be tied low on the CY7C1302V25 Address expansion for 144M. This should be tied low on the CY7C1302V25 Not Connect Pins. These are not connected to the die. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as A/C measurement points ...
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... When deselected, the write port will ignore all inputs. Single Clock Mode The CY7C1302V25 can be used with a single clock mode. In this mode the device will recognize only the pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks ...
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... Application Example Memory Controller Q Din Add. Cntr. CLK/CLK (input) CLK/CLK (output Advanced Information SRAM #4 SRAM # REF 6 CY7C1302V25 TERM REF CY7C1302V25 ...
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... A the data presented The entire 36 bits of information will then be [17:0] written into the memory array. See Write Description table for byte write information, 7 CY7C1302V25 Comments gated by the rising edge of the [17:0] . [17:0] is stored in ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG - FBGA Only) The CY7C1302V25 incorporates a serial boundary scan test access port (TAP) in the FBGA package only. The TQFP pack- age does not offer this functionality. This port operates in ac- cordance with IEEE Standard 1149 ...
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... SAMPLE / PRELOAD SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the CY7C1302V25 TAP controller is not fully 1149.1 compliant. When the SAMPLE / PRELOAD instructions is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register ...
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... TDI and TDO pins. The advan- tage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. 10 CY7C1302V25 ...
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... TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Advanced Information 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1302V25 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- ...
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... TAP Controller [ Over the Operating Range Test Conditions I = 2.0mA 100 2.0mA 100 A OL GND DDQ /2, Undershoot:V (AC)<0.5V for t<t /2, Power-up TCYC 12 CY7C1302V25 0 Selection Circuitry Min. Max. 1.7 2.1 0.7 0.2 1.7 V +0.3 DD –0.3 0 <2.6V and V <2.4V and V <1.4V for t<200 ms DDQ ...
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... CS CH 11. Test conditions are specified using the load in TAP AC test conditions. t Advanced Information [10, 11] Over the Operating Range Description /t = 1ns CY7C1302V25 Min. Max Unit 100 ns 10 MHz ...
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... TAP Timing and Test Conditions 1.25V 50W TDO = =50W 0 & =20pF L GND (a) Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Advanced Information [11] 2. TMSS t TMSH t TDIS t TDIH t TDOX 14 CY7C1302V25 ALL INPUT PULSES 1.25V t TCYC t TDOV ...
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... TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register be- tween TDI and TDO. The SAMPLEZ command implemented by the CY7C1302V25 device will place the output buffers into a HIGH-Z con- diditon. Do Not Use: This instruction is reserved for future use. ...
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... RPS 8A 36 BWS0 7B Advanced Information Boundary Scan Order (#1 Exits Device First) Bump ID Bit # Signal Name BWS1 40 WPS NC/36M(1) 44 GND/144M 45 Reserved D10 49 Q10 50 D11 51 Q11 52 D12 53 Q12 54 D13 55 Q13 56 D14 57 Q14 58 D15 59 Q15 60 D16 61 Q16 62 D17 63 Q17 CY7C1302V25 Bump (Don’t Care ...
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... Both Ports De- 6.0 ns cycle, 167 MHz DD selected 7.5 ns cycle, 133 MHz 1/t In- IL MAX CYC, puts Static 10 ns cycle, 100 MHz 17 CY7C1302V25 Ambient [13] Temperature V DD 0°C to +70°C 2.5+/–100mV 1.4V to 1.9V Min. Max. 2.4 2.6 1.4 1.9 V /2+0.3 V DDQ DDQ ...
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... Description Min. Max. [15 [15, 16] [15, 16] /I and load capacitance shown in ( test loads and t is less than t . CLZ CHZ CO 18 CY7C1302V25 -167 -133 -100 Min. Max. Min. Max. 6.0 7.5 10.0 2.4 3.2 3.5 2.4 3.2 3.5 2.7 3.3 3.4 4.1 4.4 5 ...
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... Advanced Information Test Conditions T = 25° MHz 2. 1.5V DDQ V /2 DDQ R=50W REF DDQ OUTPUT 'HYLFH 0.25V 5 pF Under 7HVW ZQ RQ= 250W INCLUDING (b) JIG AND SCOPE 19 CY7C1302V25 Max. Unit TBD pF TBD pF TBD pF [14] ALL INPUT PULSES 1.25V 0.75V ...
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... Switching Waveforms Read/Deselect Sequence t t KHKH KHKH t KHKH [17: RPS Data Out Device originally deselected. Activity on the Write Port is unknown. Advanced Information Q(A+1) Q(A) Q( KHCH t DOH DOH DON’T CARE UNDEFINED 20 CY7C1302V25 t CYC Q(B+1) Q(C+1) Q( CLZ CHZ ...
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... D(A+1) BWS is both BWS and C reference to Data Outputs and do not affect Writes. Activity on the Read Port is unknown. BWS LOW=Valid, Byte writes allowed, see Byte write table for details. x Advanced Information D(B+1) D(C) D( and BWS DON’T CARE UNDEFINED 21 CY7C1302V25 t CYC D(C+ ...
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... D(A) D(B) Write Data Forwarded Q [17: Read Port previously deselected. Any port select can deselect the port. BWS both assumed active. [1:0] Advanced Information * D(B+1) D(C) D(C+1) D(D) D(D+1) Q(E+1) Q(B+1) Q(E) Q(B) Q(G) 22 CY7C1302V25 Q(G+ UNDEFINED DON’T CARE ...
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... CY7C1302V25-167BZC/ 133 CY7C1302V25-133BZC/ 100 CY7C1302V25-100BZC/ Document #: 38-00924-** Package Diagram © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...