CY7C09389-6AC Cypress Semiconductor Corporation., CY7C09389-6AC Datasheet
CY7C09389-6AC
Specifications of CY7C09389-6AC
Related parts for CY7C09389-6AC
CY7C09389-6AC Summary of contents
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Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Six Flow-Through/Pipelined devices — 32K x 16/18 organization (CY7C09279/379) — 64K x 16/18 organization (CY7C09289/389) • Three Modes — Flow-Through — Pipelined ...
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Functional Description The CY7C09279/89 and CY7C09379/89 are high-speed syn- chronous CMOS 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. isters on control, address, ...
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... SB1 (Both Ports TTL Level) Typical Standby Current for I (mA) SB3 (Both Ports CMOS Level) Note: 8. This pin is NC for CY7C09379. Document #: 38-06040 Rev. *A 100-Pin TQFP (Top View CY7C09389 (64K x 18) CY7C09379 (32K x 18 CY7C09279/89 CY7C09279/89 CY7C09379/89 CY7C09379/89 [ 100 83 6.5 7 ...
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... DC Voltage Applied to Outputs in High Z State.................................. –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Note: 9. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 10. Industrial parts are available in CY7C09289 and Cy7C09389 only Document #: 38-06040 Rev. *A Description –A for 32K, A –A for 64K devices) ...
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Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage Min –4.0 mA Output LOW Voltage Min +4.0 mA Input HIGH Voltage ...
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AC Test Loads 893 OUTPUT 347 (a) Normal Load (Load 1) AC Test Loads (Applicable to -6 only OUTPUT 1.4V TH ...
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Switching Characteristics Over the Operating Range Parameter Description f f Flow-Through MAX1 Max f f Pipelined MAX2 Max t Clock Cycle Time - Flow-Through CYC1 t Clock Cycle Time - Pipelined CYC2 t Clock HIGH Time - Flow-Through CH1 t ...
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Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V t CYC1 t CH1 CLK R ADDRESS t CD1 DATA OUT t ...
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Switching Waveforms (continued) [19, 20] Bank Select Pipelined Read t CYC2 t t CH2 CL2 CLK ADDRESS A (B1 0(B1) DATA OUT(B1 ADDRESS A (B2) ...
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Switching Waveforms (continued) Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CL2 CLK R ADDRESS DATA IN DATA OUT ...
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Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK R ADDRESS DATA IN t CD1 ...
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Switching Waveforms (continued) Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN t t SCN HCN DATA OUT ...
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Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS n INTERNAL A n ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN ...
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Switching Waveforms (continued) [18, 30, 31, 32] Counter Reset (Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS INTERNAL A X ADDRESS SAD HAD ADS t t SCN HCN CNTEN t t SRST HRST ...
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Read/Write and Enable Operation Inputs OE CLK Address Counter Control Operation Previous Address Address CLK ADS CNTEN ...
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... Ordering Code [1] 6.5 CY7C09379-6AC 7.5 CY7C09379-7AC 9 CY7C09379-9AC 12 CY7C09379-12AC 64K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09389-6AC 7.5 CY7C09389-7AC 9 CY7C09389-9AC CY7C09389-9AI 12 CY7C09389-12AC Document #: 38-06040 Rev. *A Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack ...
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Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06040 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of ...
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Document Title: CY7C09279/89, CY7C09379/89 32K/64K X 16/18 Synchronous Dual Port Static RAM Document Number: 38-06040 Issue Orig. of REV. ECN NO. Date Change ** 110188 09/29/01 SZV *A 122290 12/27/02 RBI Document #: 38-06040 Rev. *A Description of Change Change ...