CY7C057V-15AI Cypress Semiconductor Corporation., CY7C057V-15AI Datasheet
CY7C057V-15AI
Specifications of CY7C057V-15AI
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CY7C057V-15AI Summary of contents
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... CY7C056V CY7C057V CY7C037V CY7C038V3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static RAM Features • True dual-ported memory cells that allow simultaneous access of the same memory location • 16K x 36 organization (CY7C056V) • 32K x 36 organization (CY7C057V) • 0.25-micron CMOS for optimum speed/power • ...
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... Control of a semaphore indicates that a shared resource is in use. An automatic Power-Down feature is controlled independently on each port by Chip Select (CE and CE ) pins communications The CY7C056V and CY7C057V are available in 144-Pin Thin Quad Plastic Flatpack (TQFP) and 172-Ball Ball Grid Array (BGA) packages. CY7C056V CY7C057V [3] , Page [+] Feedback ...
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... A11L A12L 31 A13L 32 [ I/O26L 34 I/O25L 35 I/O24L 36 Notes: 4. This pin is A14L for CY7C057V. 5. This pin is A14R for CY7C057V. Document #: 38-06055 Rev. *B 144-Pin Thin Quad Flatpack (TQFP) Top View CY7C056V (16K x 36) CY7C057V (32K x 36) CY7C056V CY7C057V 108 I/O33R I/O34R 107 106 I/O35R ...
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... VDD CE0R BA WA OER CE1R A8R R/WR VSS VDD VDD A10R A9R SEMR NC A12R A11R INTR A13R BUSYR [5] I/O18R I/O22R NC NC I/O6R I/O8R I/O20R I/O24R VSS NC I/O21R I/O23R CY7C056V CY7C056V CY7C057V CY7C057V -15 -20 Unit 240 230 µA 10 µA µA Page [+] Feedback ...
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... Static Discharge Voltage........................................... >2001V Latch-Up Current .................................................... >200 mA ° ° +150 C Operating Range ° ° +125 C Range Commercial Industrial +0.5V DD Shaded areas contain advance information. [7] +0.5V DD CY7C056V CY7C057V ≤ V ≥ V and Ambient Temperature V DD ° ° +70 C 3.3V ± 165 mV ° ° ...
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... Industrial Commercial 180 240 Industrial Commercial 0.01 Industrial Commercial 160 210 [10] MAX Industrial Test Conditions ° MHz 3. LOW. 1 CY7C056V CY7C057V CY7C056V CY7C057V -15 -20 2.4 2.4 0.4 0.4 0.4 2.0 2.0 0.8 0.8 0.8 10 –10 10 –10 10 240 360 230 340 mA 265 385 ...
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... External AC Test Load Capacitance = 10 pF. 13. (Internal I/O pad Capacitance = 10 pF Test Load. Document #: 38-06055 Rev. *B OUTPUT = 1.5V TH (b) Three-State Delay (Load 2) 3.0V 90% 10 ≤ 100 200 Capacitance (pF) (b) Load Derating Curve CY7C056V CY7C057V 3. 590Ω 435Ω 90% 10% ≤ Page [+] Feedback ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 20. Test conditions used are Load 1. Document #: 38-06055 Rev. *B [14] CY7C056V CY7C057V -12 -15 Min. Max. Min. Max. Min less than t and t is less than t . HZCE LZCE HZOE LZOE CY7C056V CY7C057V -20 Max. Unit time. SCE Page [+] Feedback ...
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... SEM Flag Contention Window SPS t SEM Address Access Time SAA Data Retention Mode The CY7C056V and CY7C057V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: [3] 1. Chip Enable (CE) ...
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... LZCE t ABE CHIP SELECT VALID t ACE t LZCE =V , and WA, BA are valid. This waveform cannot be used for semaphore reads transition HIGH WA, BA are valid, and SEM = access semaphore CY7C056V CY7C057V t OHA t HZCE t HZOE DATA VALID OHA t HZCE t HZCE = and SEM = Page [+] Feedback ...
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... Document #: 38-06055 Rev. *B [28, 29, 30, 31 CHIP SELECT VALID [31] t PWE [34] t HZWE t SD [28, 29, 30, 36 CHIP SELECT VALID t SCE and SEM=V and B LOW 0– PWE . CY7C056V CY7C057V [34] t HZOE LZWE NOTE allow the I/O drivers to turn off and data HZWE SD Page [+] Feedback ...
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... SPS Document #: 38-06055 Rev. *B [37] t SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [38, 39, 40] MATCH t SPS MATCH = CE = HIGH and =LOW CY7C056V CY7C057V t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...
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... Timing Diagram of Write with BUSY (M/S = HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S = LOW) R/W BUSY Note: 41 LOW HIGH Document #: 38-06055 Rev. *B [41 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C056V CY7C057V BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY will be asserted. PS Document #: 38-06055 Rev. *B [42] ADDRESS MATCH CHIP SELECT VALID t PS CHIP SELECT VALID t BLC ADDRESS MATCH CHIP SELECT VALID t PS CHIP SELECT VALID t BLC [42 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C056V CY7C057V t BHC t BHC Page [+] Feedback ...
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... Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE 3FFF (7FFF for CY7C057V CHIP SELECT VALID R/W L INT R [44] t INS Right Side Clears INT : R ADDRESS R INT R Right Side Sets INT : L ADDRESS WRITE 3FFE (7FFE for CY7C057V CHIP SELECT VALID ...
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... Architecture The CY7C056V and CY7C057V consist of an array of 16K and 32K words of 36 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE /CE 0 control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communi- cation ...
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... Left Port Writes 1 to Semaphore Right Port Writes 0 to Semaphore Right Port Writes 1 to Semaphore Left Port Writes 0 to Semaphore Left Port Writes 1 to Semaphore Notes: 45. A and A , 7FFF/7FFE for the CY7C057V. 0L–14L 0R–14R 46. If BUSY =L, then no change. R 47. If BUSY =L, then no change. L Document #: 38-06055 Rev. *B ...
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... I/O I/O Bus Match Operation The right port of the CY7C057V 32Kx36 dual-port SRAM can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data I/O. The data lines are divided into four lanes, each consisting of 9 bits (byte-size data lines). ...
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... Device operation is accomplished by treating the Word Address (WA) pin and the Byte Address (BA) pins as additional address inputs having standard cycle address and data set-up/hold times. When transferring data in byte (9-bit) bus match format, the unused I/O CY7C056V CY7C057V pins in an Upper Word/Lower Word [52] ). pins are 18R–35R ...
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... CY7C056V-15AC CY7C056V-15AXC CY7C056V-15BBC 20 CY7C056V-20AC CY7C056V-20BBC Speed (ns) Ordering Code 12 CY7C057V-12AC CY7C057V-12AXC CY7C057V-12BBC 15 CY7C057V-15AC CY7C057V-15AXC CY7C057V-15AI CY7C057V-15AXI CY7C057V-15BBC CY7C057V-15BBI 20 CY7C057V-20AC CY7C057V-20BBC Document #: 38-06055 Rev. *B Package Name Package Type A144 144-Pin Thin Quad Flat Pack A144 144-Pin Pb-Free Thin Quad Flat Pack BB172 172-Ball Ball Grid Array (BGA) ...
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... Package Diagrams 144-Pin Plastic Thin Quad Flat Pack (TQFP) A144 144-Pin Pb-Free Plastic Thin Quad Flat Pack (TQFP) A144 Document #: 38-06055 Rev. *B CY7C056V CY7C057V 51-85047-*A Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 172-Ball FBGA ( 1.25 mm) BB172 CY7C056V CY7C057V 51-85114-*B Page [+] Feedback ...
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... Document History Page Document Title: CY7C056V/CY7C057V 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static RAM Document Number: 38-06055 Issue Orig. of REV. ECN NO. Date Change ** 110214 12/16/01 *A 122305 12/27/02 *B 393770 See ECN Document #: 38-06055 Rev. *B Description of Change SZV Change from Spec number: 38-00742 to 38-06055 ...