CY7B992-7JC Cypress Semiconductor Corporation., CY7B992-7JC Datasheet
CY7B992-7JC
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CY7B992-7JC Summary of contents
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... Document Number: 38-07138 Rev. *B Programmable Skew Clock Buffer Functional Description The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high perfor- mance computer systems ...
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... GND 12 22 GND Description Table 1. “Test Mode” on page 4 under the Table 2. Table 2. Table 2. Table 2. CY7B991 CY7B992 2F0 GND 1F1 1F0 V CCN 1Q0 1Q1 GND GND Table 2. Table 2. Table 2. Table 2. “Block Diagram Description” on page 3. Page [+] Feedback ...
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... U MID MID MID HIGH Approximate HIGH LOW Which HIGH MID 22.7 HIGH HIGH 38.5 62.5 CY7B991 CY7B992 selected. U [1] Output Functions 1Q0, 1Q1, 3Q0, 3Q1 4Q0, 4Q1 3F0, 4F0 2Q0, 2Q1 –4t Divide by 2 Divide –3t –6t – –2t –4t – ...
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... HH INVERT Test Mode The TEST input is a three level input. In normal system operation, this pin is connected to ground, enabling the CY7B991 or CY7B992 to operate as explained in Matrix” on page 3. For testing purposes, any of the three level inputs can have a removable jumper to ground tied LOW through a 100Ω ...
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... Latch Up Current ..................................................... >200 mA Note 5. Indicates case temperature. Document Number: 38-07138 Rev. *B Operating Range Range ° ° +150 C Commercial Industrial ° ° +125 C [5] Military [5] Military CY7B991 CY7B992 Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° 5V ± 10% – +85 C ° ° 5V ± 10% –55 ...
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... CC all datasheet limits are achieved. 8. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must not be shorted to GND. Doing so may cause permanent damage. 9. Total output current per output pairis approximated by the following expression that includes device current plus load current: ...
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... L C (Includes fixture and probe capacitance TTL AC Test Load (CY7B991 R1=100 R2=100 (Includes fixture and probe capacitance CMOS AC Test Load (CY7B992) Document Number: 38-07138 Rev. *B Test Conditions ° MHz 5. 2.0V V =1.5V th 0.8V =30 pF for –2 and –5 devices) L 0.0V ≤1ns TTL Input Test Waveform (CY7B991) 80% =30 pF for – ...
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... VCC/2 (CY7B992). 24. tPWH is measured at 2.0V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992. 25. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8VCC and 0.2VCC for the CY7B992. ...
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... FS = HIGH 40 5.0 5.0 0.1 [16, 18] 0.25 0.6 0.5 0.5 0.5 –0.5 0.0 [22] –1.0 0.0 [23, 24] [23, 24] 0.15 1.0 0.15 1.0 [14] RMS [14] Peak-to-Peak CY7B991 CY7B992 CY7B992–5 Max Min Typ Max Unit MHz [15 5.0 ns 5.0 ns See Table 1 0.25 0.1 0.25 ns 0.5 0.25 ...
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... RMS [14] Peak-to-Peak CY7B991 CY7B992 CY7B992–7 Min Typ Max Unit MHz [15 5.0 ns 5.0 ns See Table 1 0.1 0.25 ns 0.3 0.75 ns 1.0 ...
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... AC Timing Diagrams REF OTHER Q INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 Document Number: 38-07138 Rev REF RPWL t RPWH t ODCV t ODCV t t SKEWPR, SKEWPR SKEW0,1 SKEW0,1 t SKEW2 t SKEW3,4 t SKEW3,4 t SKEW1,3, 4 CY7B991 CY7B992 SKEW2 t SKEW3,4 t SKEW2,4 Page [+] Feedback ...
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... By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. In this illustration the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes CY7B991 CY7B992 LOAD LOAD ...
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... The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15 MHz to 30 MHz CY7B991 CY7B992 40 MHz 20 MHz 80 MHz ⁄ ⁄ ...
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... Figure 7. Multi-Function Clock Driver REF INVERTED 4Q0 4Q1 3Q0 3Q1 80 MHz 2Q0 ZERO SKEW 2Q1 1Q0 1Q1 80 MHz SKEWED –3.125 ns (–4t CY7B991 CY7B992 LOAD MHz LOAD 20 MHz Z 0 LOAD Z 0 LOAD ) Page ...
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... PLL filter. Do not connect more than two clock buffers in series. Document Number: 38-07138 Rev. *B Figure 8. Board-to-Board Clock Distribution REF L1 L2 4Q0 4Q1 3Q0 3Q1 L3 2Q0 2Q1 1Q0 L4 1Q1 CY7B991 CY7B992 LOAD Z 0 LOAD Z 0 LOAD REF FS LOAD 4Q0 4F0 Z 4Q1 ...
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... CY7B992–7JC 32-Pb Plastic Leaded Chip Carrier CY7B992–7JCT 32-Pb Plastic Leaded Chip Carrier - Tape and Reel CY7B992–7JI 32-Pb Plastic Leaded Chip Carrier [27] CY7B992–7LMB 32-Pin Rectangular Leadless Chip Carrier Pb-Free 250 CY7B991–2JXC 32-Pb Plastic Leaded Chip Carrier CY7B991–2JXCT ...
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... Military Specifications Group A Subgroup Testing DC Characteristics Parameter Subgroups IHH IMM ILL IHH IMM ILL CCQ CCN Package Diagrams Figure 9. 32-Pin Plastic Leaded Chip Carrier Document Number: 38-07138 Rev. *B CY7B991 CY7B992 51-85002-*B Page [+] Feedback ...
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... Package Diagrams (continued) Figure 10. 32-Pin Rectangular Leadless Chip Carrier Document Number: 38-07138 Rev. *B MIL-STD-1835 C-12 51-85002-*B CY7B991 CY7B992 Page [+] Feedback ...
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... Document History Document Title: CY7B991/CY7B992 Programmable Skew Clock Buffer Document Number: 38-07138 Orig. of REV. ECN NO. Issue Date Change ** 110247 12/19/01 *A 1199925 See ECN KVM/AESA Add Pb-free part numbers. Update package names in Ordering Information *B 1286064 See ECN © Cypress Semiconductor Corporation, 2001-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...