CY2V9950AI Cypress Semiconductor Corporation., CY2V9950AI Datasheet

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CY2V9950AI

Manufacturer Part Number
CY2V9950AI
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY2V9950AI

Case
QFP-32L
Cypress Semiconductor Corporation
Document #: 38-07436 Rev. *A
Features
Block Diagram
• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• Output-output skew < 150 ps
• Cycle-cycle jitter < 100 ps
• Selectable positive or negative edge synchronization
• Selectable phase-locked loop (PLL) frequency range
• 8 LVTTL outputs driving 50Ω terminated lines
• LVCMOS/LVTTL Over-voltage tolerant reference input
• 2x, 4x multiply and (1/2)x, (1/4)x divide ratios
• Spread-Spectrum-compatible
• Pin-compatible with IDT5V9950 and IDT5T9950
• Industrial temperature range: –40°C to +85°C
• 32-pin TQFP package
2F1:0
3F1:0
4F1:0
1F1:0
R EF
FB
2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer
TEST
3
3
3
3
3
PLL
/ M
PE
/ K
FS
3
VDDQ 4
VDDQ 1
3901 North First Street
sO E#
VDDQ 3
1Q 0
1Q 1
2Q 0
2Q 1
3Q 0
3Q 1
4Q 0
4Q 1
Functional Description
The CY2V9950 is a low-voltage, low-power, eight-output,
200-MHz clock driver. It features functions necessary to
optimize the timing of high performance computer and
communication systems.
The user can program the output banks through 3F[0:1] and
4F[0:1]pins. Any one of the outputs can be connected to
feedback input to achieve different reference frequency multi-
plication and divide ratios and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the PE pin controls the synchro-
nization of the output signals to either the rising or the falling
edge of the reference clock.
Pin Configuration
VDDQ4
PE
VSS
4Q0
3F1
4F1
4Q1
4F0
San Jose
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
CY2V9950
,
CA 95134
Revised August 11, 2004
24
23
22
21
20
19
18
17
CY2V9950
408-943-2600
1F1
1F0
sOE#
VDDQ1
1Q0
1Q1
VSS
VSS
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CY2V9950AI Summary of contents

Page 1

Multi-Output Zero Delay Buffer Features • 2.5V or 3.3V operation • Split output bank power supplies • Output frequency range: 6 MHz to 200 MHz • Output-output skew < 150 ps • Cycle-cycle jitter < 100 ps • ...

Page 2

Pin Definitions [1] Pin Name I/O 29 REF I LVTTL/LVCMOS LVTTL 27 TEST 3-Level I 22 sOE# 2-Level LVTTL I, PU 24, 23, 26, nF[1:0] 3-Level I 25 ...

Page 3

Table 4. Frequency Range Select FS PLL Frequency Range MHz 100 MHz 200 MHz The PE pin determines whether the outputs synchronize to the rising edge or the falling edge ...

Page 4

DC Electrical Specifications @ 2.5V I 3-Level Input DC Current 3 I Input Pull-up Current PU I Input Pull-down Current PD V Output LOW Voltage OL V Output HIGH Voltage OH I Quiescent Supply Current DDQ I Dynamic Supply Current ...

Page 5

Switching Characteristics Parameter Description F Output frequency range OR VCO VCO Lock Range LR VCO VCO Loop Bandwidth LBW [9] t Matched-Pair Skew SKEWPR [9] t Output-Output Skew SKEW0 t SKEW1 t SKEW2 t SKEW3 t SKEW4 t SKEW5 t ...

Page 6

AC Timing Definitions t PWH REF OTHER Q INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 Document #: 38-07436 Rev REF t PWL t t 0DCV 0DCV t t SKEWPR SKEWPR t ...

Page 7

... LVTTL INPUT TEST WAVEFORM Ordering Information Part Number CY2V9950AC 32 TQFP CY2V9950ACT 32 TQFP – Tape and Reel CY2V9950AI 32 TQFP CY2V9950AIT 32 TQFP – Tape and Reel Document #: 38-07436 Rev. *A VDDQ 20pF Output For All Other Outputs Figure 1. t OFALL 1.7V VTH =1.25V ...

Page 8

Package Drawing and Dimensions 32-lead Thin Plastic Quad Flatpack 1.0 mm A32 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07436 Rev. *A © Cypress Semiconductor ...

Page 9

Document History Page Document Title:CY2V9950 2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer Document Number: 38-07436 REV. ECN No. Issue Date ** 122628 01/10/03 *A 252355 See ECN RGL/GGK Document #: 38-07436 Rev. *A Orig. of Change Description of Change RGL New ...

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