SAA7104E NXP Semiconductors, SAA7104E Datasheet
SAA7104E
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SAA7104E Summary of contents
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... Digital video encoder Rev. 02 — 23 December 2005 1. General description The SAA7104E; SAA7105E is an advanced next-generation video encoder which converts PC graphics data at maximum 1280 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as CVBS or S-video output ...
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... Internal Color Bar Generator (CBG) Optional support of various Vertical Blanking Interval (VBI) data insertion Macrovision Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this applies to the SAA7104E only Optional cross-color reduction for PAL and NTSC CVBS outputs Power-save modes Joint Test Action Group (JTAG) Boundary Scan Test (BST) Monolithic CMOS 3 ...
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... SAA7104E_SAA7105E_2 Product data sheet Ordering information Name Description LBGA156 plastic low profile ball grid array package; 156 balls; body 15 Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder 15 1.05 mm © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Version SOT700 ...
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... DDA3 DDA4 SSA1 A10, B9 C9, D9 C1, C2, B1, B2, A2, B4, B3, A3, F3, H1, H2, H3 PD11 to INPUT PD0 FORMATTER UPSAMPLING DECIMATOR HORIZONTAL PIXCLKI BORDER FIFO GENERATOR SAA7104E SAA7105E G4 PIXEL CLOCK CRYSTAL PIXCLKO SYNTHESIZER OSCILLATOR A5 XTALI Fig 1. Block diagram SSA2 DDD1 DDD2 DDD3 DDD4 SSD1 B8 A8 ...
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... DDA4 V SSA1 PD11 TTX_SRES SSD1 SSD2 SSD3 SSD4 GREEN_VBS_CVBS V DDA1 RESET DDD2 DDD3 DDD4 V DDA3 HSM_CSYNC TCK HSVGC Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder SAA7104E SAA7105E 001aad370 Transparent top view Pin Symbol A3 PD4 A5 XTALI A7 DUMP A9 RSET B1 PD9 B3 PD5 ...
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... C5, D5 C5, D5 C5, D5 C5, D5 Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Pin Symbol F1 VSVGC F3 PD3 F12 TVD G2 SDA G4 PIXCLKO H2 PD1 Description [2] pixel data 7 ; MSB with C -Y [2] pixel data 4 ; MSB 3 with C -Y-C B test reset input for BST; active LOW crystal oscillator input crystal oscillator output DAC reference pin ...
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... Table 12 to Table 18 for pin assignment. Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder [1] Description analog output of GREEN or VBS or CVBS signal analog output of RED CVBS signal R [3] test data output for BST reset input; active LOW test mode select input for BST digital supply voltage 2 (3 ...
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... It is also possible to encode interlaced video signals such as PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed. Besides the applications for video output, the SAA7104E; SAA7105E can also be used for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed to the DACs ...
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... HSM_CSYNC) can be generated; it can be advanced periods of the 27 MHz crystal clock in order to be adapted to the RGB processing set. The SAA7104E; SAA7105E synthesizes all necessary internal signals, color subcarrier frequency and synchronization signals from that clock. Wide screen signalling data can be loaded via the I standards using fi ...
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... Layout of a byte in the cursor bit map pixel Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder data stream. 2 C-bus control bits SLOT Section 7.10), it will sample up the data C-bus write access or can be part of the pixel data 3 bytes for the R, G and B LUT Table 8 ...
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... Cursor modes Cursor mode CMODE = 0 second cursor color first cursor color transparent inverted input -C matrix B R Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder row 0 column 1 row 0 column 5 row 0 column 9 ... row 0 column 25 row 0 column 29 ... row 31 column 25 row 31 column 29 ...
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... Philips Semiconductors If the SAA7104E; SAA7105E input data is in accordance with ‘ITU-R BT.656’ , the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur. The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange data stream at the scaler output. 7.7 Vertical scaler and anti-fl ...
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... Other manipulations used for the Macrovision anti-taping process, such as additional insertion of AGC super-white pulses (programmable in height), are supported by the SAA7104E only. To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer characteristics of the luminance interpolation fi ...
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... Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE also possible to encode closed caption data for 50 Hz field frequencies at 32 times the horizontal line frequency. 7.12.5 Anti-taping (SAA7104E only) For more information contact your nearest Philips Semiconductors sales office. SAA7104E_SAA7105E_2 Product data sheet ...
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... DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder. 7.15 HD data path This data path allows the SAA7104E; SAA7105E to be used with VGA or HDTV monitors. It receives its data directly from the cursor generator and supports RGB and Y-P output formats (RGB not with Y-P A gain adjustment either leads the full level swing to the digital-to-analog converters or reduces the amplitude by a factor of 0 ...
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... In most cases, the vertical offsets for odd and even fields are equal. If they are not, then the even field will start later. The SAA7104E; SAA7105E will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets ...
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... LINE TYPE ARRAY 15 entries event type pointer 10-bit duration 4-bit value index LINE PATTERN ARRAY 2-bit value 7 entries Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Figure 3 illustrates the line count pointer pattern pointer 10-bit duration 10-bit duration 10-bit duration ...
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... Reading of the arrays is possible but all address pointers must be initialized before the next write operation. SAA7104E_SAA7105E_2 Product data sheet SAA7104E; SAA7105E Table 9 outlines an example on how to set up the sync tables for a 1080i HD Rev. 02 — 23 December 2005 Digital video encoder © ...
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... SAA7104E_SAA7105E_2 Product data sheet value( value(3); (subtract 1 from real duration) value( value(3) value(0) + 960 value( value( value(3) value(3) + 960 value( Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder value(3) value(3) sync-black-null-black) © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... In Slave mode, the encoder receives them. The parameters of the input field are mainly given by the memory capacity of the SAA7104E; SAA7105E. The rule is that the scaler and thus the input processing needs to provide the video data in the same time frames as the encoder reads them. Therefore, the vertical active video times (and the vertical frequencies) need to be the same ...
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... OutLin – (60 Hz); FAL ------------------------------- - 2 262.5 1716 TXclk ----------------------------------------------------------------------------------- - InLin + 2 InPpl integer --------------------- - 262.5 OutLin Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder OutPix (50 Hz); 287 OutLin – (50 Hz); ------------------------------- - 2 (60 Hz) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Table ...
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... InPpl TPclk OutLin YSKIP --------------------- - 1 + 4096 ---------------- - InLin + 2 4095 Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder (50 Hz) and for the pixel clock generator Table 59 and Table 60. The divider PCLE 480 pixels resolution and 2 at resolutions FAL 1728 TXclk YOFS = -------------------------------------------------- - 2.5 InPpl TPclk © ...
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... Reference levels are measured with a color bar, 100 % white, 100 % amplitude and 100 % saturation. The SAA7104E; SAA7105E has special input cells for the VGC port. They operate at a wider supply voltage range and have a strict input threshold at speed of these cells, the EIDIV bit needs to be set to logic 1 ...
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... Pin assignment for input format 0 Falling clock edge G3/Y3 G2/Y2 G1/Y1 G0/ Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder 128 235 235 146 235 235 16 16 235 34 16 235 222 235 16 240 235 16 110 16 16 128 16 16 128) ...
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... Y0(0) B Pin assignment for input format 4 -Y-C (ITU-R BT.656, 27 MHz clock Rising clock Rising clock edge n edge 7(0) Y7( 6(0) Y6( 5(0) Y5(0) B Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Rising clock edge Rising clock edge Falling clock edge 7(0) ...
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... INDEX4 INDEX3 INDEX2 INDEX1 INDEX0 Pin assignment for input format 6 Falling clock edge G4/Y4 G3/Y3 G2/ G0/ Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder …continued Rising clock edge 0(0) R [1] Rising clock edge -Y-C B ...
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Bit allocation map Table 19: Slave receiver (slave address 88h) Register function Subaddress (hexadecimal) Status byte (read only) 00 Null Common DAC adjust fi DAC adjust coarse 17 G DAC adjust coarse 18 B ...
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Table 19: Slave receiver (slave address 88h) …continued Register function Subaddress (hexadecimal) Gain U 5B Gain V 5C Gain U MSB, black level 5D Gain V MSB, blanking level 5E CCR, blanking level VBI 5F Null 60 Standard control 61 ...
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Table 19: Slave receiver (slave address 88h) …continued Register function Subaddress (hexadecimal) TTX even request vertical start 78 TTX even request vertical end 79 First active line 7A Last active line 7B TTX mode, MSB vertical 7C Null 7D Disable ...
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Table 19: Slave receiver (slave address 88h) …continued Register function Subaddress (hexadecimal) Weighting factor even 9E Weighting factor MSB 9F Vertical line skip A0 Blank enable for NI-bypass, A1 vertical line skip MSB Border color Y A2 Border color U ...
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Table 19: Slave receiver (slave address 88h) …continued Register function Subaddress (hexadecimal) Horizontal cursor position F9 Horizontal hot spot, MSB XCP FA Vertical cursor position FB Vertical hot spot, MSB YCP FC Input path control FD Cursor bit map FE ...
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... See Table 20 for explanations. 2 C-bus write access A SUBADDRESS A Sr FEh A A RAM ADDRESS or FFh See Table 20 for explanations. 2 C-bus read access Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder A DATA 0 A ............ A DATA 00 A DATA 01 A ............ A DATA 0 A ............ A DATA 0R A DATA 0G A ...
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... DAC fine output voltage adjustment steps for all DACs 0111 7 % 0110 6 % 0101 5 % 0100 4 % 0011 3 % 0010 2 % 0001 1 % 0000 1000 0 % 1001 1 % 1010 2 % 1011 3 % 1100 4 % 1101 5 % 1110 6 % 1111 7 % Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... BCOMP R check comparator at DAC on pin BLUE_CB_CVBS 0 active, output is loaded 1 inactive, output is not loaded Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder 0.585 1111b 1.240 V at 37.5 0.585 1111b 1.240 V at 37.5 0.585 1111b 1.240 V at 37.5 © ...
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... R/W ending point of burst in clock cycles 1Dh* PAL 29; strapping pin FSVGC tied to HIGH 1Dh* NTSC 29; strapping pin FSVGC tied to LOW Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder 0* wide screen signalling output is disabled 1 wide screen signalling output is enabled 0 must be programmed with logic 0 to ensure ...
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... CVBS signal R/W 0 must be programmed with logic 0 to ensure compatibility to future enhancements Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder copy generation data output disabled enabled must be programmed with logic 0 to ensure compatibility to future enhancements LSBs of the respective bytes are encoded ...
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... Symbol Access Value Description - R/W 0 must be programmed with logic 0 to ensure compatibility to future enhancements GCD[4:0] R/W - Gain color difference of RGB (C from (1 depending on external application. Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder , Y and C ) output, ranging from Suggested nominal value = and C R ...
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... VSM provides 0* vertical sync for a monitor 1 constant signal according to GPVAL R/W 0 must be programmed with logic 0 to ensure compatibility to future enhancements Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder to RGB dematrix R © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... PAL B/G and data from look-up table 25h NTSC M and data from input ports in Master mode 46h NTSC M and data from look-up table Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder …continued Table 12 to Table 18 - fifth byte of video programming system data ...
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... IRE [4] BLNNL = 0 [4] BLNNL = 63 (3Fh) 2/6.29 + 25.4. 2/6.18 + 25.9; default after reset: 35h. Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Remarks GAINU = 2.17 nominal to +2.16 output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal GAINU = 2.05 nominal to +2.04 ...
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... NTSC (non-alternating V component) 1 PAL (alternating V component) FISE R/W total pixel clocks per line 0 864 1 858 Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder black Figure 6 and Figure 7) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Figure 8 2 C-bus address ...
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... Line 21 odd 0, 1 and even 0, 1 registers, subaddresses 67h to 6Ah, bit [1] description Symbol Access Value Description L21O[07:00] R L21O[17:10] R L21E[07:00] R L21E[17:10] R/W Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder nominal nominal nominal nominal - f = subcarrier frequency (in multiples of line fsc frequency); f ...
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... Hz, 263 lines/field non-interlaced 313 lines/field at 50 Hz, 263 lines/field Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder 00h* sets the horizontal trigger phase related to chip-internal horizontal input 0h* 00h* sets the vertical trigger phase related to chip-internal vertical input © ...
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... TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0); see 42h* if strapped to PAL 54h* if strapped to NTSC Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder - active display window horizontal start; defines the start of the active TV display portion after the border color - active display window horizontal end; ...
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... TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field, line = (TTXEVS + 4) for M-systems and line = (TTXEVS + 1) for other systems 04h* if strapped to PAL 05h* if strapped to NTSC Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Table 57) first line of occurrence of Table 57) last line of occurrence of Table 57) first line of occurrence of © ...
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... R/W see Table 52 R/W see Table 53 R/W see Table 51 Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Table 57) last line of occurrence of Table 57) first active line = (FAL + 4) for Table 57) last active line = (LAL + 3) for Figure 15) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... PIXCLK divider ratio for internal PIXCLK not allowed Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder - individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the - respective bits, disabled line = LINExx (50 Hz field rate) Description defi ...
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... Symbol Description YPIX[7:0] with YPIX[9:8] (see from the feeding device; number of requested lines = YPIX + YOFSE Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Table 66) horizontal offset; defines the number of Table 66) pixel in X direction; defines half the number Table 66) vertical offset in odd field; defines (in the Table 66) vertical offset in even fi ...
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... PCBN R/W polarity of CBO signal 0 normal (HIGH during active video) 1 inverted (LOW during active video) SLAVE R/W from the SAA7104E; SAA7105E the timing to the graphics controller is 0 master 1 slave ILC R/W if hardware cursor insertion is active 0 set LOW for non-interlaced input signals ...
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... Vertical increment register, subaddress 9Bh, bit description Symbol Description YINC[7:0] with YINC[11:8] (see number of active output lines engine; YINC = --------------------------------------------------------------------- - number of active input lines Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder …continued Table 71) horizontal length; – line Table 74) incremental fraction of the horizontal scaling line line Table ...
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... R/W 000 YSKIP[11:8] R/W Border color Y register, subaddress A2h, bit description Symbol Description BCY[7:0] luminance portion of border color in underscan area Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Table 77) weighting factor for the first line YINC YIWGTO = ------------- - + 2048 2 Table 77) weighting factor for the first line YINC YSKIP – ...
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... The value 0 means that the entry is not used. Layout of the data bytes in the line type array Description 0 HLP12 HLP11 0 HLP32 HLP31 0 HLP52 HLP51 0 HLP72 HLP71 Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder HLC4 HLC3 HLC2 HLC1 HLT0 0 0 HLC9 HLP10 0 HLP02 HLP01 HLP30 0 ...
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... Layout of the data bytes in the value array Description HPVE7 HPVE6 HPVE5 sync trigger state 1 register, subaddress D4h, bit description Description Table backwards) Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder HPD04 HPD03 HPD02 HPD01 HPV00 0 0 HPD09 HPD14 HPD13 HPD12 ...
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... HDSYE R/W HD sync engine 0* off 1 active HDTC R/W HD output path processes 0* RGB 1 YUV Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Table 94) state of the HD duration counter after trigger © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Symbol Description YHS[4:0] vertical hot spot of cursor 2 - must be programmed with logic 0 to ensure compatibility to future enhancements 1 and 0 YCP[9:8] vertical cursor position YCP[7:0] Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder …continued © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... CURSA Table 105: Color look-up table register, subaddress FFh, bit description Data byte COLSA In subaddresses 5Bh, 5Ch, 5Dh, 5Eh, 62h and D3h all IRE values are rounded up. SAA7104E_SAA7105E_2 Product data sheet SAA7104E; SAA7105E Access Value Description color look-up table 0 active 1 bypassed ...
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... Table 108: Chip ID register, subaddress 1Ch, bit description Bit Symbol Access Value Description CID[7:0] R SAA7104E_SAA7105E_2 Product data sheet SAA7104E; SAA7105E Access Value Description 101 version identification of the device: it will be changed with all versions of the IC that have different programming models; current version is 101 binary ...
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... FIFO underflow 1 FIFO underflow has occurred; this bit is reset after this subaddress has been read (1) ( Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder (MHz) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. mbe737 ...
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... CCRS[1:0] = 11. (4) CCRS[1:0] = 00. Fig 8. Luminance transfer characteristic 1 (excluding scaler) SAA7104E_SAA7105E_2 Product data sheet (dB 0.4 6 (4) 0 ( Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder mbe735 (1) (2) 0.8 1.2 1.6 f (MHz) ( (MHz) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. mgd672 ...
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... Fig 9. Luminance transfer characteristic 2 (excluding scaler) G (dB) Fig 10. Luminance transfer characteristic in RGB (excluding scaler) SAA7104E_SAA7105E_2 Product data sheet (dB Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder mbe736 ( (MHz © Koninklijke Philips Electronics N.V. 2005. All rights reserved. mgb708 14 f (MHz ...
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... XTALI, SDA and SCL input voltage at digital inputs or I/O pins voltage difference between V and V SSA(n) SSD(n) storage temperature ambient temperature electrostatic discharge voltage Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Conditions Min 0.5 0.5 0.5 0.5 outputs in 3-state ...
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... To minimize the effective R th(j-a) connected to the power and ground layers directly. An ample copper area directly under the SAA7104E; SAA7105E with a number of through-hole plating, connected to the ground layer (four-layer board: second layer), can also reduce the effective R use any solder-stop varnish under the chip ...
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... C load capacitance L R series resistance S C motional capacitance 1 (typical) C parallel capacitance 0 (typical) SAA7104E_SAA7105E_2 Product data sheet SAA7104E; SAA7105E Conditions V = 1.1 V, 1 2.5 V DDD1 V = 3.3 V DDD1 pins TDO, TTXRQ_XCLKO2, VSM and HSM_CSYNC V = 1.1 V, 1 2.5 V DDD1 V = 3.3 V DDD1 pins TDO, TTXRQ_XCLKO2, VSM ...
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... TDO, TTXRQ_XCLKO2, VSM and HSM_CSYNC see Table 113 see Table 113 see Table 113 see Table 113 100 mV for HIGH and 2 DDD2 with R = 37.5 and (typical). L ext Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Min Typ Max 1 1.23 - ...
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... Product data sheet t HIGH t t d(CLKD HD;DAT t t o(d) t o(h) CBO PD XOFS IDEL CBO YOFS Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder T PIXCLK HD;DAT t SU;DAT SU;DAT XPIX HLEN YPIX © Koninklijke Philips Electronics N.V. 2005. All rights reserved 0.5V DDD1 V OL ...
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... TTX data; it has a constant length Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder = 9.78 s (PAL 10.5 s (NTSC) TTX TTX 2 C-bus register settings. t i(TTXW © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... DGND 0 MHz XTALI XTALO DDD4 SAA7104E SAA7105E RSET SSD4 SSA 1 k AGND AGND Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder 3.3 V analog supply 0.1 F AGND use one capacitor for each V DDA DDA1 DDA3 VSM, HSM_CSYNC GREEN_VBS_CVBS FLTR0 75 AGND AGND ...
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... Philips Semiconductors Fig 17. FLTR0, FLTR1 and FLTR2 of SAA7104E_SAA7105E_2 Product data sheet SAA7104E; SAA7105E C16 120 pF L2 2.7 H C10 C13 390 pF 560 pF AGND JP11 JP12 FIN FILTER 1 = byp. ll act. Figure 16 Rev. 02 — 23 December 2005 Digital video encoder L3 2.7 H FOUT mhb912 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Due to 2 C-bus settings of the DAC reference currents (analog Table 37 to Table 41 for example a standard PAL or NTSC signal) Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder SAA7104E SAA7105E A5 A6 XTALI XTALO 27.00 MHz ...
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... Table 41 see Table 37 to 881 e.g. G DAC = 1Bh 1.00 V (p-p) (ferrite coil) in each digital supply line close to the decoupling capacitors to Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Table 113, standard compliant RGB, black-to-white Table 41 see Table 31 and Table 32 876 e ...
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... Test information 13.1 Boundary scan test The SAA7104E; SAA7105E has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7104E; SAA7105E follows the ‘IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture’ ...
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... The device identification register contains 32 bits, numbered where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Figure a. SAA7104E. b. SAA7105E. Fig 19. 32 bits of identification code SAA7104E_SAA7105E_2 Product data sheet 19 ...
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... Product data sheet 1 1 scale 15.2 15 0.25 14.8 14.8 REFERENCES JEDEC JEITA MO-192 - - - Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder detail 0.12 0.35 0.1 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT700-1 ISSUE DATE 01-05-11 01-11- ...
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... For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; SAA7104E_SAA7105E_2 Product data sheet SAA7104E; SAA7105E 2 called small/thin packages. Rev. 02 — 23 December 2005 Digital video encoder ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 02 — 23 December 2005 SAA7104E; SAA7105E Digital video encoder Soldering method Wave not suitable [4] not suitable suitable [5] [6] not recommended [7] not recommended not suitable © ...
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... The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors • Table • Package outline changed from SOT472-1 to SOT700-1 SAA7104E_SAA7105E_1 20040304 SAA7104E_SAA7105E_2 Product data sheet SAA7104E; SAA7105E Product data sheet CPCN 200505019 4: updated description for pin E2 Product - specification Rev. 02 — 23 December 2005 Digital video encoder ...
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... For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com SAA7104E_SAA7105E_2 Product data sheet SAA7104E; SAA7105E [2] [3] Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. ...
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... Video path 7.12.2 Teletext insertion and encoding (not simultaneously with real-time control 7.12.3 Video Programming System (VPS) encoding. 14 7.12.4 Closed caption encoder . . . . . . . . . . . . . . . . . 14 7.12.5 Anti-taping (SAA7104E only 7.13 RGB processor . . . . . . . . . . . . . . . . . . . . . . . . 15 7.14 Triple DAC 7.15 HD data path 7.16 Timing generator 7.17 Pattern generator for HD sync pulses ...