ISP1561BM NXP Semiconductors, ISP1561BM Datasheet
ISP1561BM
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ISP1561BM Summary of contents
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ISP1561 Hi-Speed Universal Serial Bus PCI Host Controller Rev. 02 — 5 March 2007 1. General description The ISP1561 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) Host Controller. It integrates two Original USB Open Host Controller ...
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... NXP Semiconductors 2. Features I Complies with I Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) I Two Original USB OHCI cores are compliant with Interface Specification for USB” I One Hi-Speed USB EHCI core is compliant with Interface Specification for Universal Serial Bus” ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name ISP1561BM LQFP128 ISP1561_2 Product data sheet Description plastic low profile quad flat package; 128 leads; body 14 Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Version 14 1.4 mm SOT420-1 © NXP B.V. 2007. All rights reserved. ...
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... OC2 OC3 AMB2 AMB3 GRN2 GRN3 GL2 GL3 PWE2 PWE3 DM2 DP1 DP2 7 ISP1561BM IRQ1 8 IRQ12 12 KBIRQ1 13 MUIRQ12 11 A20OUT 6, 14, 21, 29, 37, 45, 53, DGND 61, 69, 76, 83, 86, 128 SEL2 9 PORTS EHCI (FUNCTION 2) ...
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... SEL48M SCL SDA PME# V AUX DGND IRQ1 IRQ12 SEL2PORTS V DD ISP1561_2 Product data sheet 1 ISP1561BM 32 Pin description Pin Type Description 1 I selection between 12 MHz crystal and 48 MHz oscillator 0 — 12 MHz crystal is used 1 — 48 MHz oscillator is used push-pull; TTL with hysteresis tolerant ...
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... NXP Semiconductors Table 2. Symbol A20OUT KBIRQ1 MUIRQ12 DGND SMI# INTA RST# CLK GNT# DGND REQ# AD[31] AD[30 AD[29] AD[28] AD[27] DGND AD[26] AD[25] AD[24 C/BE#[3] IDSEL AD[23] DGND AD[22] AD[21] AD[20] ISP1561_2 Product data sheet Pin description …continued [1] Pin Type Description ...
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... NXP Semiconductors Table 2. Symbol V DD AD[19] AD[18] AD[17] DGND AD[16] C/BE#[2] FRAME IRDY# TRDY# DEVSEL# DGND STOP# CLKRUN# PERR SERR# PAR C/BE#[1] DGND AD[15] AD[14] AD[13 AD[12] AD[11] AD[10] DGND AD[9] AD[8] C/BE#[0] ISP1561_2 Product data sheet Pin description …continued [1] Pin ...
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... NXP Semiconductors Table 2. Symbol V DD AD[7] AD[6] DGND AD[5] AD[4] AD[ AD[2] AD[1] DGND AD[0] V AUX DGND XTAL1 XTAL2 OC1 PWE1 GL1 AMB1 AV AUX GND_RREF GRN1 OC2 PWE2 ISP1561_2 Product data sheet Pin description …continued [1] Pin Type Description 73 - supply voltage (3 I/O bit 7 of multiplexed PCI address and data ...
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... NXP Semiconductors Table 2. Symbol GL2 AMB2 GRN2 AV AUX_PLL DM1 DP1 AGND OC3 PWE3 RREF AV AUX DM2 DP2 AGND GL3 AMB3 GRN3 AV AUX DM3 DP3 AGND OC4 ISP1561_2 Product data sheet Pin description …continued [1] Pin Type Description 98 O GoodLink LED indicator output for USB downstream port 2 (open-drain) ...
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... NXP Semiconductors Table 2. Symbol PWE4 AV AUX DM4 DP4 AGND GL4 AMB4 GRN4 DGND [1] Symbol names ending with a ‘#’ (for example, NAME#) represent active LOW signals for PCI pins. Symbol names with an overscore (for example, NAME) represent active LOW signals for USB pins. ...
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... NXP Semiconductors 7. Functional description 7.1 OHCI Host Controller An OHCI Host Controller transfers data to devices at the Original USB defined bit rate of 12 Mbit/s or 1.5 Mbit/s. 7.2 EHCI Host Controller The EHCI Host Controller transfers data to a Hi-Speed USB compliant device at the Hi-Speed USB defined bit rate of 480 Mbit/s. When the EHCI Host Controller has the ownership of a port, OHCI Host Controllers are not allowed to modify the port register. All additional port bit defi ...
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... NXP Semiconductors 7.6 Power management The ISP1561 provides an advanced power management capabilities interface that is compliant with controlled and managed by the interaction between drivers and PCI registers. For a detailed description on power management, see 7.7 Legacy support The ISP1561 provides legacy support for a USB keyboard and mouse. This means that the keyboard and mouse must be able to work even before the OS boot-up, with the necessary support in the system’ ...
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... NXP Semiconductors 8.1.2 PCI initiator and target A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI transactions as a slave. In the ISP1561, the two open Host Controllers and the enhanced Host Controller function as both initiators or targets of PCI transactions issued by the host CPU ...
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... Table 5 Value Description [1] X Device ID: This register value is defined by NXP Semiconductors to identify the USB Host Controller IC product. For the ISP1561, NXP Semiconductors has defined OHCI functions as 1561h, and the EHCI function as 1562h. Rev. 02 — 5 March 2007 HS USB PCI Host Controller … ...
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... NXP Semiconductors 8.2.1.3 Command register (address: 04h) This is a 2-byte register that provides coarse control over the ability of a device to generate and respond to PCI cycles. The bit allocation of the Command register is given in Table the PCI bus for all accesses, except configuration accesses. All devices are required to support this base level of functionality ...
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... NXP Semiconductors Table 7. Bit 8.2.1.4 Status register (address: 06h) The Status register is a 2-byte read-only register used to record status information on PCI bus-related events (bit allocation: see Table 8. Status register: bit allocation Bit 15 Symbol DPE SSE Reset 0 Access R Bit 7 Symbol FBBC reserved ...
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... NXP Semiconductors Table 9. Bit ISP1561_2 Product data sheet Status register: bit description Symbol Description DPE Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if the parity error handling is disabled. SSE Signaled System Error: This bit must be set whenever the device asserts SERR# ...
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... NXP Semiconductors 8.2.1.5 Revision ID register (address: 08h) This 1-byte read-only register indicates a device-specific revision identifier. The value is chosen by the vendor. This field is a vendor-defined extension of the device ID. The Revision ID register bit description is given in Table 10. Revision ID register: bit description ...
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... NXP Semiconductors 8.2.1.7 CacheLine Size register (address: 0Ch) The CacheLine Size register is a read/write single-byte register that specifies the system cacheline size in units of DWORDs. This register must be implemented by master devices that can generate the Memory Write and Invalidate command. The value in this register is also used by master devices to determine whether to use the Read, Read Line, or Read Multiple command to access memory ...
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... NXP Semiconductors 8.2.1.10 BIST register (address: 0Fh) This register is used for control and status of Built In Self Test (BIST). Devices that do not support BIST must always return logic 0, that is, treat reserved register. A device whose BIST is invoked must not prevent normal operation of the PCI bus. The BIST register is not used in the ISP1561 ...
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... Table 19. Value Description [1] X Subsystem ID: For the ISP1561, NXP Semiconductors has defined OHCI functions as 1561h, and the EHCI function as 1562h. Value Description DCh Capabilities Pointer: EHCI manages power efficiently using this register. This power management register is allocated at offset DCh. Only one Host Controller is needed to manage power in the ISP1561 ...
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... NXP Semiconductors 8.2.1.18 Interrupt Pin register (address: 3Dh) This 1-byte register is use to specify which interrupt pin the device or device function uses. The bit description is given in Devices or functions that do not use an interrupt pin must put a logic 0 in this register. Table 22. Interrupt Pin register: bit description ...
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... NXP Semiconductors 8.2.2 Enhanced Host Controller-specific PCI registers In addition to the PCI configuration header registers, EHCI needs some additional PCI configuration space registers to indicate the serial bus release number, downstream port wake-up event capability, and adjust the USB bus frame length for Start-Of-Frame (SOF). ...
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... NXP Semiconductors Table 29. FLADJ value : 31(1Fh) 32 (20h (3Eh) 63 (3Fh) 8.2.2.3 PORTWAKECAP register (address: 62h) The PORTWAKECAP register is a 2-byte register, and the bit description is given in Table 30. This register is used to establish a policy about which ports are for wake events. Bit positions the mask correspond to a physical port implemented on the current EHCI controller ...
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... NXP Semiconductors 8.2.3.2 NEXT_ITEM_PTR register (address: value read from address 34h + 1h) The Next Item Pointer (NEXT_ITEM_PTR) register (see of the next item in the function’s capability list. The value given is an offset into the function’s PCI configuration space. If the function does not implement any other capabilities defi ...
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... NXP Semiconductors Table 35. Bit The logic level of the AMB4 pin at power-on determines the default value of PMC registers. If this pin is connected to V the case of notebook design). If this pin is left open or is pulled down, then the ISP1561 does not support D3 8.2.3.4 PMCSR register (address: value read from address 34h + 4h) ...
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... NXP Semiconductors Table 36. PMCSR register: bit allocation Bit 15 Symbol PMES [1] Reset X Access R/W Bit 7 Symbol Reset 0 Access - [1] Sticky bit, if the function supports PME# from D3 function does not support PME# from D3 Table 37. Bit ISP1561_2 Product data sheet DS[1: R reserved then X is indeterminate at the time of initial operating system boot the cold ...
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... NXP Semiconductors Table 37. Bit 8.2.3.5 PMCSR_BSE register (address: value read from address 34h + 6h) The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI bridge-specific functionality and is required for all PCI-to-PCI bridges. The bit allocation of this register is given in Table 38. PMCSR_BSE register: bit allocation ...
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... NXP Semiconductors Table 40. Originating device’s bridge PM state hot D3 cold 8.2.3.6 Data register (address: value read from address 34h + 7h) The Data register is an optional, 1-byte register that provides a mechanism for the function to report state dependent operating data, such as power consumed or heat dissipated ...
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... NXP Semiconductors C-bus interface A simple I product ID and some other configuration bits from an external EEPROM. 2 The I C-bus interface is for bidirectional communication between ICs using two serial bus wires: SDA (data) and SCL (clock). Both lines are driven by open-drain circuits and must be connected to the positive supply voltage through pull-up resistors ...
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... Information loading from EEPROM Figure 4 default values of Device ID (DID), Vendor ID (VID), subsystem VID and subsystem DID assigned to NXP Semiconductors by PCI-SIG will be loaded. See value. For instructions on programming the EEPROM, refer to application note “Designing a Hi-Speed USB Host PCI Adapter Using the ISP1561” ...
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... NXP Semiconductors 10.2 USB bus states Reset state — When the USB bus is in the reset state, the USB system is stopped. Operational state — When the USB bus is in the active state, the USB system is operating normally. Suspend state — When the USB bus is in the suspend state, the USB system is stopped. Resume state — ...
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Table 42. USB Host Controller registers Address OHCI register (Hex) Func0 OHCI1 (2 ports) 00 HcRevision 0000 0110 04 HcControl 0000 0000 08 HcCommandStatus 0000 0000 0C HcInterruptStatus 0000 0000 10 HcInterruptEnable 0000 0000 14 HcInterruptDisable 0000 0000 18 HcHCCA ...
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Table 42. USB Host Controller registers …continued Address OHCI register (Hex) Func0 OHCI1 (2 ports) 104 HceInput 0000 0000 108 HceOutput 0000 0000 10C HceStatus 0000 0000 [1] Reset values that are highlighted (for example, 0) are the ISP1561 implementation ...
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... NXP Semiconductors For the OHCI Host Controller, these registers are divided into two types: one set of operational registers for the USB operation and one set of legacy support registers for the legacy keyboard and mouse operation. For the enhanced Host Controller, there are two types of registers: one set of read-only capability registers and one set of read/write operational registers ...
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... NXP Semiconductors Table 44. Bit 11.1.2 HcControl register (address: content of the base address register + 04h) The HcControl register defines the operating modes for the Host Controller. All the fields in this register, except HCFS and RWC, are modified only by the HCD. The bit allocation is given in Table 45 ...
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... NXP Semiconductors Table 46. Bit ISP1561_2 Product data sheet HcControl register: bit description Symbol Description - reserved RWE Remote Wake-up Enable: This bit is used by the HCD to enable or disable the remote wake-up feature on detecting upstream resume signaling. When this bit and the RD bit in HcInterruptStatus are set, a remote wake-up is signaled to the host system ...
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... NXP Semiconductors Table 46. Bit 11.1.3 HcCommandStatus register (address: content of the base address register + 08h) The HcCommandStatus register is used by the Host Controller to receive commands issued by the HCD. It also reflects the current status of the Host Controller. To the HCD, it appears as a “write to set” register. The Host Controller must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register ...
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... NXP Semiconductors Table 47. HcCommandStatus register: bit allocation Bit 31 Symbol Reset 0 Access - Bit 23 Symbol Reset 0 Access - Bit 15 Symbol Reset 0 Access - Bit 7 Symbol Reset 0 Access - Table 48. Bit ISP1561_2 Product data sheet reserved reserved reserved reserved HcCommandStatus register: bit description Symbol Description - reserved SOC[1:0] Scheduling Overrun Count: The bit is incremented on each scheduling overrun error ...
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... NXP Semiconductors Table 48. Bit 1 0 11.1.4 HcInterruptStatus register (address: content of the base address register + 0Ch) This is a 4-byte register that provides the status of the events that cause hardware interrupts. The bit allocation of the register is given in Host Controller sets the corresponding bit in this register. When a bit becomes set, a ...
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... NXP Semiconductors Bit 7 Symbol reserved RHSC Reset 0 Access - R/W Table 50. Bit 11.1.5 HcInterruptEnable register (address: content of the base address register + 10h) Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. If the following conditions occur: • ...
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... NXP Semiconductors Then, a hardware interrupt is requested on the host bus. Writing logic bit in this register sets the corresponding bit, whereas writing logic bit in this register leaves the corresponding bit unchanged read, the current value of this register is returned. The bit allocation is given in Table 51. ...
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... NXP Semiconductors Table 52. Bit 11.1.6 HcInterruptDisable register (address: content of the base address register + 14h) Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Therefore, writing logic bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas writing logic bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged ...
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... NXP Semiconductors Table 54. Bit 11.1.7 HcHCCA register (address: content of the base address register + 18h) The HcHCCA register contains the physical address of Host Controller Communication Area (HCCA). The bit allocation is given in restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The alignment is evaluated by examining the number of zeroes in the lower order bits. The minimum alignment is 256 bytes ...
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... NXP Semiconductors Table 55. HcHCCA register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access - Table 56. Bit 11.1.8 HcPeriodCurrentED register (address: content of the base address register + 1Ch) The HcPeriodCurrentED register contains the physical address of the current isochronous or interrupt ED ...
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... NXP Semiconductors Bit 7 Symbol Reset 0 Access R Table 58. Bit 11.1.9 HcControlHeadED register (address: content of the base address register + 20h) The HcControlHeadED register contains the physical address of the first ED of the control list. The bit allocation is given in Table 59. HcControlHeadED register: bit allocation Bit ...
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... NXP Semiconductors 11.1.10 HcControlCurrentED register (address: content of the base address register + 24h) The HcControlCurrentED register contains the physical address of the current ED of the control list. The bit allocation is given in Table 61. HcControlCurrentED register: bit allocation Bit 31 Symbol Reset 0 Access R Bit 23 Symbol Reset ...
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... NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W Table 64. Bit 11.1.12 HcBulkCurrentED register (address: content of the base address register + 2Ch) This register contains the physical address of the current endpoint of the bulk list. ...
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... NXP Semiconductors Table 66. Bit 11.1.13 HcDoneHead register (address: content of the base address register + 30h) The HcDoneHead register contains the physical address of the last completed TD that was added to the done queue normal operation, the HCD need not read this register because its content is periodically written to the HCCA. ...
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... NXP Semiconductors 11.1.14 HcFmInterval register (address: content of the base address register + 34h) The HcFmInterval register contains a 14-bit value that indicates the bit time interval in a frame, that is, between two consecutive SOFs, and a 15-bit value indicating the full-speed maximum packet size that the Host Controller may transmit or receive, without causing a scheduling overrun ...
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... NXP Semiconductors 11.1.15 HcFmRemaining register (address: content of the base address register + 38h) The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame. Table 71. HcFmRemaining register: bit allocation Bit 31 Symbol FRT Reset 0 Access R/W Bit 23 Symbol Reset ...
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... NXP Semiconductors Bit 23 Symbol Reset 0 Access - Bit 15 Symbol reserved Reset 0 Access - Bit 7 Symbol Reset 0 Access R/W R/W Table 74. Bit 11.1.17 HcPeriodicStart register (address: content of the base address register + 40h) The HcPeriodicStart register has a 14-bit programmable value that determines when is the earliest time for the Host Controller to start processing the periodic list. The bit allocation is given in Table 75 ...
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... NXP Semiconductors Bit 7 Symbol Reset 0 Access R/W R/W Table 76. Bit 11.1.18 HcLSThreshold register (address: content of the base address register + 44h) This register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8-byte low-speed packet before EOF. Neither the Host Controller nor the HCD can change this value ...
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... NXP Semiconductors Table 78. Bit 11.1.19 HcRhDescriptorA register (address: content of the base address register + 48h) The HcRhDescriptorA register is the first of two registers describing the characteristics of the root hub. Reset values are implementation-specific. Table 79 Table 79. HcRhDescriptorA register: bit allocation Bit 31 Symbol Reset ...
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... NXP Semiconductors Table 80. Bit 11.1.20 HcRhDescriptorB register (address: content of the base address register + 4Ch) The HcRhDescriptorB register is the second of two registers describing the characteristics of the root hub. The bit allocation is given in initialization to correspond with the system implementation. Reset values are implementation-specific. ...
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... NXP Semiconductors Table 81. HcRhDescriptorB register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W Table 82. Bit 11.1.21 HcRhStatus register (address: content of the base address register + 50h) The HcRhStatus register is divided into two parts. The lower word of a DWORD represents the Hub Status fi ...
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... NXP Semiconductors Table 83. HcRhStatus register: bit allocation Bit 31 Symbol CRWE Reset 0 Access R/W Bit 23 Symbol Reset 0 Access - Bit 15 Symbol DRWE Reset 0 Access R/W Bit 7 Symbol Reset 0 Access - Table 84. Bit ISP1561_2 Product data sheet reserved reserved HcRhStatus register: bit description Symbol Description ...
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... NXP Semiconductors Table 84. Bit 11.1.22 HcRhPortStatus[1:4] register (address: content of the base address register + 54h) The HcRhPortStatus[1:4] register is used to control and report port events on a per-port basis. NumberofDownstreamPort represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word reflects the port status. The upper word refl ...
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... NXP Semiconductors Table 86. Bit ISP1561_2 Product data sheet HCRhPortStatus[1:4] register: bit description Symbol Description - reserved PRSC Port Reset Status Change: This bit is set at the end of the 10 ms port reset signal. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. 0 — ...
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... NXP Semiconductors Table 86. Bit ISP1561_2 Product data sheet HCRhPortStatus[1:4] register: bit description Symbol Description PPS On read Port Power Status: This bit reflects the port power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. The HCD can set this bit by writing Set Port Power or Set Global Power ...
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... NXP Semiconductors Table 86. Bit 11.2 USB legacy support registers The ISP1561 supports legacy keyboard and mouse. Four operational registers are used to provide the legacy support. Each of these registers is located on a 32-bit boundary. The offset of these registers is relative to the base address of the Host Controller operational registers with HceControl located at offset 100h ...
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... NXP Semiconductors Table 87. Offset 100h 104h 108h 10Ch Table 88. I/O address 60h 60h 64h 64h 11.2.1 HceControl register (address: content of the base address register + 100h) Table 89 Table 89. HceControl register: bit allocation Bit 31 Symbol Reset 0 Access - Bit 23 Symbol Reset 0 Access - Bit 15 Symbol ...
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... NXP Semiconductors Table 90. Bit 11.2.2 HceInput register (address: content of the base address register + 104h) The HceInput register is a 4-byte register, and the bit allocation is given in I/O data that is written to ports 60h and 64h is captured in this register, when emulation is enabled. This register may directly be read or written by accessing it in the Host Controller’ ...
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... NXP Semiconductors Bit 23 Symbol Reset 0 Access - Bit 15 Symbol Reset 0 Access - Bit 7 Symbol Reset 0 Access R/W R/W Table 92. Bit 11.2.3 HceOutput register (address: content of the base address register + 108h) Data placed in this register by the emulation software is returned when I/O port 60h is read and emulation is enabled read of this location, the OUT_FULL (Output Full) bit in HceStatus is set to logic 0 ...
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... NXP Semiconductors Table 94. Bit 11.2.4 HceStatus register (address: content of the base address register + 10Ch) The contents of the HceStatus register are returned on an I/O read of port 64h when emulation is enabled. Reads and writes of port 60h, and writes to port 64h can cause changes in this register. Emulation software can directly access this register through its memory address in the Host Controller’ ...
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... NXP Semiconductors Table 96. Bit 11.3 EHCI controller capability registers Other than the OHCI Host Controller, there are some registers in EHCI that define the capability of EHCI. The address range of these registers is located before the operational registers. 11.3.1 CAPLENGTH/HCIVERSION register (address: content of the base address ...
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... NXP Semiconductors Table 98. Bit 11.3.2 HCSPARAMS register (address: content of the base address register + 04h) The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that are structural parameters. The bit allocation is given in Table 99. HCSPARAMS register: bit allocation Bit 31 Symbol Reset 0 Access ...
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... NXP Semiconductors Table 100. HCSPARAMS register: bit description Bit 11.3.3 HCCPARAMS register (address: content of the base address register + 08h) The Host Controller Capability Parameters (HCCPARAMS) register is a 4-byte register, and the bit allocation is given in Table 101. HCCPARAMS register: bit allocation Bit ...
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... NXP Semiconductors Bit 15 Symbol Reset 0 Access - Bit 7 Symbol Reset 0 Access R Table 102. HCCPARAMS register: bit description Bit 11.4 Operational registers of enhanced USB Host Controller 11.4.1 USBCMD register (address: content of the base address register + 0Ch) The USB Command (USBCMD) register indicates the command to be executed by the serial Host Controller ...
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... NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access - Bit 7 Symbol LHCR IAAD Reset 0 Access R/W R/W Table 104. USBCMD register: bit description Bit ISP1561_2 Product data sheet ITC[7: R/W R reserved ASE PSE R/W R/W Symbol Description - reserved ITC[7:0] Interrupt Threshold Control: Default 08h. This fi ...
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... NXP Semiconductors Table 104. USBCMD register: bit description Bit ISP1561_2 Product data sheet Symbol Description IAAD Interrupt on Asynchronous Advance Doorbell: This bit is used as a doorbell by software to notify the Host Controller to issue an interrupt the next time it advances the asynchronous schedule. Software must write logic 1 to this bit to ring the doorbell ...
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... NXP Semiconductors 11.4.2 USBSTS register (address: content of the base address register + 10h) The USB Status (USBSTS) register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software clears the register bits by writing ones to them. The bit allocation is given in Table 105 ...
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... NXP Semiconductors Table 106. USBSTS register: bit description Bit ISP1561_2 Product data sheet Symbol Description HCH HC Halted Default. This bit is logic 0 when the Run/Stop bit of the USBCMD register is logic 1. The Host Controller sets this bit to logic 1 after it has stopped executing because the Run/Stop bit is set to logic 0, either by software or by the Host Controller hardware ...
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... NXP Semiconductors 11.4.3 USBINTR register (address: content of the base address register + 14h) The USB Interrupt Enable (USBINTR) register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in the USBSTS to allow the software to poll for events ...
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... NXP Semiconductors Table 108. USBINTR register: bit description Bit 11.4.4 FRINDEX register (address: content of the base address register + 18h) The Frame Index (FRINDEX) register is used by the Host Controller to index into the periodic frame list. The register updates every 125 s, once each microframe. Bits are used to select a particular entry in the periodic frame list during periodic schedule execution ...
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... NXP Semiconductors Table 110. FRINDEX register: bit description Bit Table 111. N based value of FLS[1:0] FLS[1:0] 00b 01b 10b 11b 11.4.5 CTRLDSSEGMENT register (address: content of the base address register + 1Ch) The Control Data Structure Segment (CTRLDSSEGMENT) register corresponds to the most significant address bits (bits 63 to 32) for all EHCI data structures. If the 64AC (64-bit Addressing Capability) fi ...
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... NXP Semiconductors Table 112. PERIODICLISTBASE register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access - Table 113. PERIODICLISTBASE register: bit description Bit 11.4.7 ASYNCLISTADDR register (address: content of the base address register + ...
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... NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol LPL[2:0] Reset 0 Access - Table 115. ASYNCLISTADDR register: bit description Bit 11.4.8 CONFIGFLAG register (address: content of the base address register + 4Ch) The bit allocation of the Configure Flag (CONFIGFLAG) register is given in Table 116. CONFIGFLAG register: bit allocation ...
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... NXP Semiconductors 11.4.9 PORTSC registers (address: content of the base address register + 50h + (4 times Port Number The Port Status and Control (PORTSC) register (bit allocation: auxiliary power well only reset by hardware when the auxiliary power is initially applied or in response to a Host Controller reset. The initial conditions of a port are: • ...
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... NXP Semiconductors Table 119. PORTSC register: bit description Bit PTC[3: PIC[1: LS[1:0] ISP1561_2 Product data sheet Symbol Description Port Test Control: Default = 0000b. When this field is logic 0, the port is not operating in test mode. A nonzero value indicates that it is operating in test mode and test mode is indicated by the value. The encoding of test mode bits are: 0000b — ...
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... NXP Semiconductors Table 119. PORTSC register: bit description Bit ISP1561_2 Product data sheet Symbol Description - reserved PR Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not in reset. Default = 0. When software sets this bit from logic 0, the bus reset sequence as defi ...
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... NXP Semiconductors Table 119. PORTSC register: bit description Bit [1] These fields read logic 0, if the Port Power (PP) (bit 12 in register PORTSC 1,2,3,4) is logic 0. ISP1561_2 Product data sheet Symbol Description FPR Force Port Resume: Logic 1 means resume detected or driven on the port. Logic 0 means no resume (K-state) detected or driven on the port. Default = ...
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... NXP Semiconductors 12. Current consumption Table 120 SEL2PORTS pin is connected to V Table 120. Current consumption when SEL2PORTS is HIGH Cumulative current Total current on pins V plus AV AUX plus AV plus V AUX_PLL DD Auxiliary current on pins V plus AUX AV plus AV AUX AUX_PLL On pin V DD [1] When one or two full-speed or low-speed power devices are connected, the current consumption is comparable with the current consumption when no high-speed devices are connected ...
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... NXP Semiconductors Table 121. Current consumption when SEL2PORTS is LOW Cumulative current On pin V DD [1] When one to four full-speed or low-speed power devices are connected, the current consumption is comparable with the current consumption when no high-speed devices are connected. There is a difference of only about 3 mA. ...
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... NXP Semiconductors 13. Limiting values Table 123. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V auxiliary voltage AUX AV analog auxiliary voltage (3.3 V); AUX supply voltage AV analog auxiliary voltage (3.3 V); AUX_PLL supply voltage for PLL ...
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... NXP Semiconductors 15. Static characteristics Table 125. Static characteristics 3 3 +85 C; unless otherwise specified. DD amb Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL V hysteresis voltage hys V LOW-level output voltage OL Table 126. Static characteristics: digital pins +85 C; unless otherwise specified. ...
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... NXP Semiconductors Table 128. Static characteristics: USB interface block (pins DM1 to DM4 and DP1 to DP4 3 3 +85 C; unless otherwise specified. DD amb Symbol Parameter V high-speed disconnect detection HSDSC threshold voltage (differential signal amplitude) V high-speed data signaling common HSCM mode voltage range (guideline for ...
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... NXP Semiconductors 16. Dynamic characteristics Table 129. Dynamic characteristics: system clock timing +85 C; unless otherwise specified. DD amb Symbol Parameter Crystal oscillator f clock frequency clk External clock input clock duty cycle External clock input J external clock jitter t rise time CR t fall time ...
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... NXP Semiconductors Table 132. Dynamic characteristics: high-speed source electrical characteristics +85 C; unless otherwise specified. DD amb Symbol Parameter Z driver output impedance HSDRV (which also serves as high-speed termination) Clock timing t high-speed data rate HSDRAT t microframe interval HSFRAM t consecutive microframe HSRFI interval difference Table 133 ...
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... NXP Semiconductors 16.1 Timing Table 135. PCI clock and IO timing Symbol Parameter PCI clock timing; see Figure 5 T CLK cycle time cyc t CLK HIGH time high t CLK LOW time low SR CLK slew rate CLK SR RST# slew rate RST# PCI input timing; see ...
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... NXP Semiconductors CLK input delay Fig 6. PCI input timing CLK output delay output Fig 7. PCI output timing T PERIOD 3.3 V crossover point differential data lines the bit duration corresponding with the USB data rate. PERIOD Full-speed timing symbols have a subscript prefix ‘F’, low-speed timings a prefix ‘L’. ...
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... NXP Semiconductors 17. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 pin 1 index 128 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 18. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 10. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 138. Abbreviations Acronym DID EHCI EMI EOF HC HCCA HCD HCI OHCI PMC ...
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... NXP Semiconductors [3] ISP1561 Evaluation Board User’s Guide — UM10005 [4] Open Host Controller Interface Specification for USB — Rev. 1.0a [5] PCI Bus Power Management Interface Specification — Rev. 1.1 [6] PCI Local Bus Specification — Rev. 2.2 [7] The I [8] Universal Serial Bus Specifi ...
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... NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Symbols and descriptions have been updated, wherever applicable, to comply with the new identity guidelines of NXP Semiconductors. • Updated • Table 2 “Pin Updated I/O detail of pin SERR#. ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. PCI configuration space registers of OHCI1, OHCI2 and EHCI . . . . . . . . . . . . . . . . . . . . . . .13 Table 4. Vendor ID register: bit description . . . . . . . . . .14 Table 5. Device ID register: bit description . . . . . . . . . .14 Table 6. Command register: bit allocation . . . . . . . . . . .15 Table 7. Command register: bit description . . . . . . . . . .15 Table 8. Status register: bit allocation . . . . . . . . . . . . . .16 Table 9 ...
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... NXP Semiconductors Table 96. HceStatus register: bit description . . . . . . . . . .65 Table 97. CAPLENGTH/HCIVERSION register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Table 98. CAPLENGTH/HCIVERSION register: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Table 99. HCSPARAMS register: bit allocation . . . . . . . .67 Table 100.HCSPARAMS register: bit description . . . . . . .67 Table 101.HCCPARAMS register: bit allocation . . . . . . . .68 Table 102.HCCPARAMS register: bit description . . . . . . .69 Table 103.USBCMD register: bit allocation . . . . . . . . . . .69 Table 104 ...
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... NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 3. EEPROM connection diagram . . . . . . . . . . . . . . .30 Fig 4. Information loading from EEPROM . . . . . . . . . . .31 Fig 5. PCI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Fig 6. PCI input timing . . . . . . . . . . . . . . . . . . . . . . . . . .91 Fig 7. PCI output timing . . . . . . . . . . . . . . . . . . . . . . . . .91 Fig 8. USB source differential data-to-EOP transition skew and EOP width . . . . . . . . . . . . . . . . . . . . . .91 Fig 9. ...
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... NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . 11 7.1 OHCI Host Controller . . . . . . . . . . . . . . . . . . . 11 7.2 EHCI Host Controller . . . . . . . . . . . . . . . . . . . 11 7.3 Dynamic port-routing logic . . . . . . . . . . . . . . . 11 7.4 Hi-Speed USB analog transceivers . . . . . . . . 11 7 ...
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... NXP Semiconductors 11.1.10 HcControlCurrentED register (address: content of the base address register + 24h 11.1.11 HcBulkHeadED register (address: content of the base address register + 28h 11.1.12 HcBulkCurrentED register (address: content of the base address register + 2Ch 11.1.13 HcDoneHead register (address: content of the base address register + 30h ...