PXB4350E Infineon Technologies AG, PXB4350E Datasheet
PXB4350E
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PXB4350E Summary of contents
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ICs for Communications ATM OAM Processor AOP PXB 4340 E Version 1.1 Data Sheet 04.2000 DS 1 ...
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... Critical components of Infineon Technologies AG, may only be used in life-support devices or systems express written approval of Infineon Technologies AG critical component is a component used in a life-support device or system whose failure can reasonably be ex- pected to cause the failure of that life-support device or system affect its safety or effectiveness of that device or system ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Cell Filter 1 and 2 Registers (CTRxy, MRxy 3.3 Transmit / ...
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Test Register 1 (TESTR1 ...
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Layer Point Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1: Chipset configuration for main ATM layer functionality . . . . . . . . . . . . . . . . . . . 11 Figure 2: Chipset configuration for main ATM layer functionality plus full ...
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Figure 47: Setup and Hold Time Definition (Single- and Multi-PHY 158 Figure 48: Tristate Timing (Multi-PHY, Multiple Devices Only ...
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Table 1: OAM Functionality Determined by Layer Point Configuration . . . . . . . . . . . . . . 19 Table 2: AOP Register Overview . . . . . . . . . . . ...
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The PXB 4340 E ATM OAM Processor is a member of the Infineon ATM622 chip set. The whole chip set consists of: • PXB 4330 E ATM Buffer Manager ABM • PXB 4340 E ATM OAM Processor AOP • PXB ...
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Conn. RAM UTOPIA PXB 4350 E PHYs Conn. RAM UTOPIA PXB 4350 E PHYs Data Sheet Pol. Conn. RAM RAM UTOPIA PXB 4340 E ALP AOP Conn. Conn. RAM RAM Pol. CAME Conn. RAM RAM UTOPIA PXB 4340 E ALP ...
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The ATM 622 Layer devices can be used as .... ...a full switch in: ADSL Concentrators / Multiplexers (DSLAM) Access Multiplexers Access Concentrators Multiservice switches ...Line card in: Workgroup Switches Edge Switches Core Switches UTOPIA Data Sheet UTOPIA 1-13 UTOPIA ...
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UTOPIA UTOPIA Due to their most flexible scaling facilities, feature set and throughput the Infineon ATM622 layer chips are the ideal devices for almost any ATM system. Data Sheet UTOPIA 1-14 04.2000 ...
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Performance up to STM-4/OC-12 equivalent ATM layer processing • Flexibel throughput from1 .. 687 Mbit/s bi-directional • 16384 connections in both directions (VPC/ VCC) • Temperature range from 0°C to 70°C • Multiport UTOPIA Level 2 interface ...
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Automatic generation of VC-AIS cells for all VCCs of a VPC at the endpoint including automatic backward emission of VP-RDI cells • Automatic generation of VP/VC-CC cells to detect ATM layer failures • Optional internal CC function for switch ...
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Data Sheet 1-17 04.2000 ...
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The PXB 4340 AOP is located at the ports of a switch so that each ATM cell passes two PXB 4340 AOP devices, one at the ingress port and one at the egress port. The PXB 4340 AOP assumes that ...
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This concept is introduced to enable the automatic execution of OAM functions by the AOP. For each connection, VPC or VCC the layer point is configured at connection setup. Then the OAM functions required for this layer point are executed ...
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In the following scenarios examples for four layer point configurations are shown. In these figures a switch with its incoming and outgoing port is represented by the symbol shown in . The PXB 4340 AOP can be configured according to ...
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In a heterogeneous network containing ATM and non-ATM interfaces VCC origination or termination occurs at the AAL function, as e.g. Circuit Emulation Service (CES) with AAL1 or Segmentation and Reassembly (SAR) with AAL5 as shown in The PXB 4340 AOP ...
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The PXB 4340 AOP provides full standardized OAM functionality of the ATM layer in one device, covering the functions Fault Management (AIS, RDI, CC, LB) and Performance Monitoring (FM flow, BR flow, Data Collection). It has STM-4/OC-12 equivalent throughput in ...
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Each cell entering the PXB 4340 AOP via the upstream/downstream receive UTOPIA interface is identified either as user cell or as OAM cell. The chip recognizes all standardized OAM cells and has two programmable comparators for possible new OAM cell ...
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BR cell from downstream 2 LB cell from downstream 3 FM cell from downstream 4 scan poll 5 scan OAM insertion 6 µP cell insertion 7 µP RAM access (RMW) 8 utopia highest priority ...
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The downstream transmit buffer has 2 thresholds for each queue: • the UTOPIA backpressure threshold: beyond this threshold the backpressure signal is given to the downstream receive interface for this PHY (see • the OAM cell insertion threshold: beyond this ...
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The external RAMs for the storage of connection related OAM data are symmetrical in up- and downstream direction. Also the addressing is symmetrical as the LCI values for forward and backward connection are identical. Note that according to the standards ...
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There are two groups of applications for OAM functions: alarms and measurements. Alarm functions inform users and network operators about network failures. These include the OAM functions • Alarm Indication Signal (AIS) • Remote Defect Indication (RDI) • Continuity Check ...
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F4/F5 processing (see and downstream direction; up- and downstream direction). Otherwise all F4/F5 cells are discarded at the receiving point. The PXB 4340 AOP automatically inserts VP-AIS cells for VPCs and VC-AIS cells for VCCs. shows that this case occurs ...
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F4 originating end point RDI cell F5 RDI cell AOPE configured terminating end point for all VCCs in one VPC: F5 AIS cells are sent • Discard of VP-AIS cells ...
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Setup of a new connection Normal Operation One valid user cell or one CC cell or if Terminating CC is disabled: no AIS cell is received for a certain time (programmable <= 3,5 sec, default 2,5 sec) notification to uP ...
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The actual F5-AIS/RDI state is indicated by bits 14..19 in Dword2 of the downstream external Ram entry ( page 102). For the actual F4-AIS/RDI state information use bits 22..27 in Dword4 of the downstream external RAM entry ( entry ( ...
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Port b VCCb Port a VCCa configured intermediate point and originating segment point 1 F4 user cells 2 F4 RDI cell F5 RDI cell F5 RDI cell AOPE configured intermediate point and terminating segment ...
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CC inactive At the CC termination point (see • discard of CC cells (see • declaration of LOC 3.5 seconds absence of user or OAM cells (see • declaration of LOC setup of new connetion CC ...
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To further limit the load for the microprocessor the DMA function is provided which transfers relevant status bits for all connections to the control processor memory in the background (see ). The insertion of AIS cells occurs as in the ...
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There are three possibilities for specifying the loopback point cell: • End-to-end LB processing • Segment LB processing • End Point LB processing The loopback function determines which loopback activities are executed dependent on ATM layer configuration ...
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F4 originating end point and F5 orginating end point F5 originating segment point 1 4 AOPE AOPE LB status = 1 configured as an configured terminating end point and F5 terminating ...
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F4 originating end point and F5 orginating end point F5 originating segment point AOPE AOPE LB status = 1 configured as an configured terminating end point and ...
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If the LB indication cell is equal to 1 and an LB location ID of the LB cell is equal to the network element ID (LB location ID match) the LB indication flag is set to 0 ...
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VPCI consistency check is supported by the LB function at the VPC terminating end point. The loopback function of AOPE (upstream) indicates ’VPCI consistency’ by setting a ...
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The first BR cell is generated when the first FM cell for this PM flow has been received. This BR cell carries valid data to initialize the BR data collection point, but no valid data for data collection. Only the ...
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AOP Note that between Nodes ’a’ and ’b’ a number of intermediate nodes can be located. All PXB 4340 AOP chips on these nodes must be configured either as Originating or Terminating Segment Points (OSP, TSP Intermediate Points ...
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The data collection procedure is independent of the FM/BR cell mechanism. It uses one of the 128 data collection processors contained in the PXB 4340 AOP. Each of them can evaluate the BR data flow from upstream or downstream direction. ...
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Common flow (CLP = 0+1) (-2,X) TUCdiff BLER0 not defined SECB = severely errored cell block MLOST = 3 .... (-4,X) (-3,X) Add 1 to SECB Add |TUCdiff| to TLOSTC Add 1 to IMPB The PXB 4340 AOP ...
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The arbitrary assignment of PM processors to connections also allows e.g. to terminate a Segment PM flow and generate a new Segment PM flow for the same connection within one PXB 4340 AOP as shown in Segment FM flow Segment ...
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X. Consequently the AIS analyser implementation totally ignores SCC/ ICC cells. Neither the occurrence of SCC/ICC cells causes return to AIS normal state nor the setup for activation of the CC checker disables return to ...
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The PXB 4340 AOP provides two types of cell filters: • filters for special OAM cells • filters for general purpose ATM cells For both filter types two filters are provided. For these filters only the first payload byte of ...
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The microprocessor can not access these RAMs directly, but uses a transfer register set. It consists of three blocks: • read register block • write register block • mask register block. In addition an address register specifying the entry to ...
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This mechanism has to be triggered by the microprocessor recommended to trigger 0.5 s time frame, as all time-out values are determined based on this time interval. During a SCAN all entries within the specified ...
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For the DMA data transfers a 32 word FIFO is provided on-chip for DMA read (figure 31 emptied by the microprocessor via consecutive reads of the DMA register. The DMA request pin of the PXB 4340 AOP is ...
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WDR0L Write Data Register 0 (15 WDR0H Write Data Register 0 (31..16) 02 WDR1L Write Data Register 1 (15 WDR1H Write Data Register 1 (31..16) 04 WDR2L Write Data Register 2 (15 WDR2H ...
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WDR13H Write Data Register 13 (31..16) 1C RDR0L Read Data Register 0 (15 RDR0H Read Data Register 0 (31..16) 1E RDR1L Read Data Register 1 (15 RDR1H Read Data Register 1 (31..16) 20 RDR2L Read ...
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MDR0H Mask Data Register 0 (31..16) 3A MDR1L Mask Data Register 1 (15 MDR1H Mask Data Register 1 (31..16) 3C MDR2L Mask Data Register 2 (15 MDR2H Mask Data Register 2 (31..16) 3E MDR3L Mask ...
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CTR20 6E CTR21 6F CTR22 70 MR10 71 MR11 72 MR12 73 MR20 74 MR21 75 MR22 80 TXR0 Transmit Cell Register 0 (Header) 81 TXR1 Transmit Cell Register 1 (Header) 82 TXR2 Transmit Cell Register 2 (Header) 83 ...
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B0 DWDRL DMA Write-Register (15..0) B1 DWDRH DMA Write-Register (31..16) B2 DMRL DMA Mask-Register (15 DMRH DMA Mask-Register (31..16) B4 PHYERRL Port 15..0 upstream only B5 PHYERRH Port 23..16 upstream only B6 DMAR DMA-Register of DMA-FIFO B7 DCONF ...
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D0 ISR0 Interrupt Status Register 0 D1 ISR1 Interrupt Status Register 1 D2 IMR0 Interrupt Mask Register 0 D3 IMR1 Interrupt Mask Register 1 D4 CIFL Cell Insertion Fault Port bit map D5 CIFH E0 UTCONF0 Config. UTOPIA ATM side ...
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F0 MISC SW reset, 1Mbit/2Mbit RAM F1 TESTR1 F2 TESTR2 F3 VERL Version register (15 VERH Version register (31..16) F5 BISTML BIST Mode Low register F6 BISTMH BIST Mode High register F7 BISTDON F8 BISTERR Data Sheet rw, ...
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These registers are provided for data transfer to and from the external connection RAMs or the internal RAMs.Two internal RAMs are provided, one for PM data processing and one for the collection of analysed PM results. Both PM RAMs are ...
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Read Transfer Read Transfer Registers RDR H L The address of the selected entry is given in register RMWADR. Register bits for specifying the target RAM and initiating the transfer are contained in the read-modify-write control register RMWC. This ...
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Read/write Address 00 ..1B H Value after reset 0000 H The write transfer registers are shown below with their mapping to the 32-bit Dwords 0..13. Register WDR13H / Address 1B 13 Register WDR12H / Address 19 12 Register WDR11H / ...
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Read Address 1C .. Value after reset 0000 H The read transfer registers are shown below with their mapping to the 32-bit Dwords 0..13. Register RDR13H / Address 37 13 Register RDR12H / Address 35 12 Register RDR11H ...
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The mask data registers are shown below with their mapping to the 32-bit Dwords 0..6. Register MDR6H / Address 45 6 Register MDR5H / Address 43 5 Register MDR4H / Address 41 4 Register MDR3H / Address 3F 3 Register ...
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Read/write Address 47 H Value after reset 0000 H Unused RAMSEL(1:0) Select RAM for RMW access START Command bit. Set =1 to start the RMW-access specified with bits 2, 4 and 5. Bit 3 is reset after ...
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Read/write Address 48 H Value after reset 0000 H Unused ADR(13:0) Specifies the base address for the RMW access. In 4x1M mode the bits 13..12 selects the RAM, the bits 11..0 defines the address. In 2x2M mode the bit 13 ...
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Read/write Address 60 ..67 H Value after reset 0000 H 60 LSIDR0 61 LSIDR1 62 LSIDR2 63 LSIDR3 64 LSIDR4 65 LSIDR5 66 LSIDR6 67 LSIDR7 The 16-octet Port ID defines a unique identifier for the switch port ...
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ACTION(1:0) Action in case of cell filter match OAMTYP(3:0) Defines the OAM Type bits of the OAM cell to be filtered. FUNCTYP(3:0) Defines the Function Type bits of the OAM cell to be filtered. Read/write Address ...
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Programming of the two cell filters is identical: VPI/LCI 1 MR10 1 CTR10 2 MR20 2 CTR20 Only the 5 MSBs of the UDF1 octet are compared. The 3 LSBs are treated like masked and match always. In case of ...
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These registers are used to insert ATM cells into the cell stream and to extract or copy cells from the cell stream. For the insertion one set of 27 registers (TXR0...TXR26) is provided capable of storing a complete ATM cell ...
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Read/write Address 83 ...9A H Value after reset 0000 (for all TXR3 84 TXR4 85 TXR5 86 TXR6 87 TXR7 88 TXR8 89 TXR9 8A TXR10 8B TXR11 8C TXR12 8D TXR13 8E TXR14 8F TXR15 90 TXR16 ...
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Read/write Address 9C H Value after reset 0000 H Unused ENCRC Enable automatic CRC-10 generation of inserted cell 0 1 TXUP Writing this bit to 1 initiates insertion of the cell specified in registers 80...9A into upstream data path. Insertion ...
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Read Address 9D H Value after reset 0000 H RXRCEL(15:0) Receive Cell Buffer access. A cell extracted or copied from the data stream is transferred from the internal receive buffer to the microprocessor by 27 read accesses of RXRCEL. The ...
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These registers define the thresholds in the PM data collection algorithm described in The referenced counters are located in the PM Data Collection RAM (see Read/write Address A0 H Value after reset 0000 H Recommended value 0003 . H UMLOST(15:0) ...
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Read/write Address A4 H Value after reset 0000 H Recommended value 0003 . H DMLOST(15:0) holds the global MLOST threshold (CLP0+1 cells) for the PM data collection in downstream direction block with more than MLOST lost cells is ...
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The SCAN performs the OAM functions AIS, RDI and CC for all connections. It must be triggered by the microprocessor in 500 ms intervals. The SCAN procedure goes through all requested entries of the external connection memory, reads the data ...
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Read/write Address B0 H Value after reset 0000 H DWDRL(15:0) DMA Write Register(15:0), specifies the lower 16-bit of the Dword to be written into the external connection RAM via DMA. The bit positions to be overwritten in the connection RAM ...
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Read/write Address B2 H Value after reset 0000 H DMRL(15:0) DMA Mask Register(15:0 Read/write Address B3 H Value after reset 0000 H DMRH(15:0) DMA Mask Register(31:16 Data Sheet DMRL(15:8) DMRL(7:0) Bit is unchanged. Bit is replaced ...
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Read/write Address B4 H Value after reset 0000 H PHYERRL(15:0) These bits have a one-to-one correspondence with the PHYs that are connected to the switch port. In case of an interruption of the physical transmission (e.g. laser failure) the microprocessor ...
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Read Address B6 H Value after reset 0000 H DMAR(15:0) DMA Read Register of DMA-FIFO (32 words deep). The external DMA controller has to be programmed to read this address. Read/write Address B7 H Value after reset 0000 H Unused ...
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DMAEN Enable MPDREQ output signal MODE Selects standard DMA or compressed DMA 0 1 INDEX(2:0) Selects which word (0..7) in the LCI table is object of the RMW operation of standard DMA. INDEX is don’t care in compressed ...
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Read/write Address B9 H Value after reset 0057 H F4F5 PROP Unused IDLEMAX(2:0) F4F5PROP Control forced AIS/RDI cell generation (ARINS bit in external RAM) behaviour at F4TEP IDLEMAX(2:0) Time for transition from AIS defect/failure to normal operation or ...
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Read/write Address BB H Value after reset 0000 H Unused Unused DMAUP Select SCAN with DMA transfer upstream. OAMUP Select SCAN with OAM processing upstream. DMADN Select SCAN with DMA transfer downstream. OAMDN Select SCAN with OAM processing downstream. STARTSC ...
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Read/write Address BD H Value after reset 0000 H Unused LCIMAX(13:0) Upper boundary of LCI range processed by SCAN (up- and downstream). Read only Address BE H Value after reset 0000 H Unused Unused CGENP Upstream cell generation pending, internal ...
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Read only Address BF H Value after reset 8000 DMA buffer empty = 0 words in FIFO. DF DMA buffer full LCIS(13:0) Currently processed LCI up- and downstream. Internal state for debugging. Interrupt bits signal unpredictable ...
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Read/write Address D0 H Value after reset 0000 H Bit 15 UUPED Bit 14 DUPED Bit 13 UUSOCE Bit 12 DUSOCE Bit 11 UEDCER Bit 10 DEDCER Bit 9 RXCEL Bit 8 RXOV Bit 7 OCIF Bit 6 Is set ...
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Bit 4 DBERR (Bit 3..0) These bits indicate important transitions of AIS, RDI or CC state diagrams (see respective functionality enabled. These are collection interrupts of the respective connection specific flags in the external RAM: Bit 3 DCSTTR Bit 2 ...
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Read/write Address D2 H Value after reset 0000 H IMR0(15:0) Interrupt mask register for ISR0 Read/write Address D3 H Value after reset 0000 H IMR1(8:0) Interrupt mask register for ISR1 Read Address D4 H Value after ...
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Read Address D5 H Value after reset 0000 H CIF(23:0) For the respective Port 15..0 in downstream direction an OAM cell could not be inserted. This occurs during the SCAN process if between consecutive LCIs there is no opportunity to ...
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Read/write Address E0 H Value after reset 0000 H This register configures the ATM side UTOPIA interfaces. Unused Bit (15:5) Unused UTA16 Select 8- or 16-bit UTOPIA Data bus 0 1 UTAPAR Enables/disables parity check 0 1 Bit (2) Unused ...
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Read/write Address E1 H Value after reset 0000 H This register configures the PHY side UTOPIA interfaces and the defines the LCI location. Unused Bit(15:10) Unused LCIMOD(1:0) Position of LCI up/downstream Bit(7:5) Unused UTP16 Select 8- ...
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Read/write Address E2 H Value after reset 0000 H Read/write Address E3 H Value after reset 0000 H Bit(15:8) Unused UPRTEN(23:16 Read/write Address E4 H Value after reset 0000 H Data Sheet UPORTEN(15:8) UPORTEN(7:0) Unused UPRTEN(23:16) Disables UTOPIA ...
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Read/write Address E5 H Value after reset 0000 H Bit(15:0) Unused DPRTEN(23: Read/write Address E6 H Value after reset 001E H Unused OAMTHRU(5:0) Threshold for forced OAM cell insertion in upstream direction. If the upstream 32-cell buffer is ...
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Read/write Address E7 H Value after reset 0060 H Unused OAMTHRD(6:0) Threshold for forced OAM cell insertion in downstream direction queue of the downstream shared buffer is filled beyond this level OAM cells destined to the respective PHY ...
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Read/write Address F0 H Value after reset 0000 H Unused RAMSEL(1:0) Selects the type of RAM used for upstream and downstream external connection RAM SWRES SW-reset. If set to one the internal reset cycle is executed. Read/write Address ...
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Unused(15:3) TINT Test of Interrupt write: 2. write: ... 10. write: 11. write: ... 16. write: 17. write: ... 32. write: Bit TINT has to be set to ’0’ to re-enter normal operation. LOOPUD 1 LOOPDU 1 ...
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Read Address F3 H Value after reset A06D H Read Address F4 H Value after reset 523B ...
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Read/write Address F5 H Value after reset 0000 H RXR UTTXD1 Bit coding(1:0) Selects the BIST function RXR Select BIST function for Receive Buffer NCP Select BIST function for Cell Processing RAM UTTXD1..3 Select BIST function ...
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Bit coding(1:0) Selects the BIST function PMDC6..0 Select BIST function for PM data collection RAM part 6..0 PMAIN Select BIST function for PM main RAM Read Address F7 H Value after reset 0000 H The 16 ...
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Read Address F8 H Value after reset 0000 H The 16 bits of this register have a one-to-one correspondence with internal RAM blocks. These bits are set if during BIST execution an error occured in the respective RAM block. Bit ...
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CEDCID(6: CTSDCID(6: 30.. Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always ...
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Bit 24 DISF5 0 1 Bit 23 CTSP 0 1 Bit 22 COSP 0 1 Bit 21 Unused It is recommended to initialize with ’0’. Bit 20 CIP 0 1 Bit 19 VCON 0 1 LCI2(13:0)18..5 Pointer to the VP ...
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Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Bit 30..15 Initialize connection setup. Do not change by µP in normal operation. Bit 14 CICCEN 1 Bit 13 CSCCTEN ...
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Bit 6 CARIEN 0 1 Bit 5 CLOCFAI F5 LOC failure state indication. Initialize connection setup. Do not change by µP in normal operation. Bit 4 CLOCDEF F5 LOC defect state indication. Initialize connection ...
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Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. 30..27 Unused It is recommended to initialize with ’0’. CTSDCID(6:0) Identifier for Data Collection on terminated / intermediate Segment F5 BR cells. Related ...
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Bit 13 EDCERR 1 Bit 12 OAMMIS 1 Bit 11..7 Initialize connection setup. Do not change by µP in normal operation. Bit 6 CCCINS 0 1 Bit 5 Initialize connection setup. Do not change ...
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Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Bit 30 CEDCEN Enable Data Collection on F5 End-to-End BR cells. Related identifier CEDCID. Bit 29 CSDCEN Enable Data Collection on F5 Segment ...
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Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Bit 30 PPMTEN Enable a terminating F4 Segment or End-to-End FM flow. Flow type selected with PMFT in PM RAM entry. Related identifier ...
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Bit 22 PAISD2F 1 Bit 21 PLBS F4 Loopback State according to I.610. Should be set before inserting a LB cell, cleared after reception of the looped cell. Bit 20 VPCCHK VPCI consistency check. If set indicates that a LB ...
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Bit 7 Initialize connection setup. Do not change by µP in normal operation. Bit 6 PARINS 1 Bit 5 Initialize connection setup. Do not change by µP in normal operation. Bit 4..0 Initialize to ...
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Bit 8 PAISMEN 0 1 Bit 7 PCCMEN 0 1 Bit 6 PARIEN 0 1 Bit 5 PLOCFAI 1 Bit 4 PLOCDEF 1 Bit 3 PRDIFAI 1 Bit 2 PRDIDEF 1 Bit 1 PAISFAI 1 Bit 0 PAISDEF 1 Data ...
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Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Bit 30 PEDCEN Enable Data Collection on F4 End-to-End BR cells. Related identifier PEDCID. Bit 29 PSDCEN Enable Data Collection on F4 Segment ...
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CEDCID(6: CTSDCID(6: 30.. Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. ...
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Bit 24 DISF5 0 1 Bit 23 CTSP 0 1 Bit 22 COS 0 1 Bit 20 CIP 0 1 Bit 19 VCON 0 1 LCI2(13:0) Pointer to the VP connection data of the actual VCC. F4 pointer in register ...
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Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Bit 30..15 Initialize connection setup. Do not change by µP in normal operation. Bit 14 CICCEN 1 Bit 13 CSCCTEN ...
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Bit 7 CCCMEN 0 1 Bit 6 CARIEN 0 1 Bit 5 CLOCFAI F5 LOC failure state. Initialize connection setup. Do not change by µP in normal operation. Bit 4 CLOCDEF F5 LOC defect state. Initialize to ...
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Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. CTSDCID(6:0) Identifier for Data Collection on terminated / intermediate F5 Segment BR cells. Related enable is CTSDCEN in Dword3. Bit 19 CLOCF2N 1 ...
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Bit 12 OAMMIS 1 Bit 11..7 Initialize connection setup. Do not change by µP in normal operation. Bit 6 CCCINS 0 1 Bit 5 Initialize connection setup. Do not change by µP in normal ...
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PEDCID(6: 30.. Bit 31 PAR Dword parity protection. In normal operation write to ...
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Bit 24 PRDID2F 1 Bit 23 PAISF2N 1 Bit 22 PAISD2F 1 Bit 21 PLBS F4 Loopback State according to I.610. Should be set before inserting a LB cell, cleared after reception of the looped cell. Bit 20 Reserved, set ...
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Bit 13 PIP 0 1 Bit 12..9 Initialize connection setup. Do not change by µP in normal operation. Bit 8 PCCINS 1 Bit 7 Initialize connection setup. Do not change by µP in normal ...
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Bit 9 PRDIMEN 0 1 Bit 8 PAISMEN 0 1 Bit 7 PCCMEN 0 1 Bit 6 PARIEN 0 1 Bit 5 PLOCFAI 1 Bit 4 PLOCDEF: 1 Bit 3 PRDIFAI: 1 Bit 2 PRDIDEF: 1 Bit 1 PAISFAI: 1 ...
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Bit 0 PAISDEF: 1 Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Bit 30 PEDCEN Enable Data Collection on F4 End-to-End BR cells. Related identifier PEDCID. Bit 29 PSDCEN Enable Data ...
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FMDIFF(15:0) 1 BIP16(15:0) 0 TUC(15:0) Bit 31:16 TUC(15:0) Total user cell count high and low priority cells (CLP0+1). Used at originating and terminating point. Initialized to all set-up. Bit 15:0 TUC0(15:0) Total user cell count high ...
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Bit 31:16 FMDIFF(15:0) Local TUC minus TUC from incoming FM cell at FM terminating point. FMDIFF is not used at FM originating point. Initialized to all set- up. Bit 15:12 Block length encoding. Programmed by the microprocessor, ...
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Bit 9 Unused Bit 8 BRIDIS 0 1 Bit(7:0) Unused TUCOLD(15:0) 0 TRCCOLD(15:0) TRCCOLD(15:0) Offset values : used for TUCDiff calculation. TRCC0OLD(15:0) Offset values : used ...
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Bit 31 FBR Set after the 1. BR cell, no Data Collection is done for 1. BR cell. SECB(30:0) Total severely errored cell blocks. ERRC(31:0) Total errored cells. LOSTC(31:0) Total lost cells (CLP = 0+1). LOSTC0(31:0) Total lost cells (CLP ...
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TLOSTC0(31:0) Total lost cells (CLP = 0). SECBERR(31:0) Total severely errored cell blocks due to bit errors. SECBMIS(31:0) Total severely errored cell blocks due to misinserted cells. Data Sheet 3-125 04.2000 ...
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This section describes the actions to be done by the microprocessor. For this purpose the following network scenario is assumed (see also • The OAM functions AIS/RDI/CC are always enabled for all connections (although the AOP also supports enabling on ...
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RMW cycle is lost during write-only-access (bit 0 of register RMWC equal to ’1’). During read or modify the external RAM parity-check will be done. While RMW is active, the registers RMWC and RMWADR are writeprotected. ...
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These are the actions to be performed after reset to prepare the AOP for operation. • Check reset values of all registers • Set HW configuration (RAM type, UTOPIA configuration) • Initialize internal and external RAMs For this purpose the ...
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This command is issued by the microprocessor either on request from the system controller or in the course of a activation/deactivation cell received for this connection. The following parameters are needed: • LCI of the connection or LCI2 of the ...
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Up - ’0’ : ...
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CRDIF2N F5 10 CRDID2F F5 9 CAISF2N F5 8 CAISD2F F5 7 ’0’ always - 6 ’0’ always - 5 CLOCFAI F5 4 CLOCDEF F5 3 CRDIFAI F5 2 CRDIDEF F5 1 CAISFAI F5 0 CAISDEF F5 1) Refer ...
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The transmission cell is usually initiated by the system controller. The parameters • LCI • segment or end-to-end or intra-domain LB • the Location identifier in case of intra-domain LB must be given by the system controller. ...
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In this example a VPC containing a VCC is terminated. A number of PM measurements are performed: • end-to-end (VPC) level bi-directional • segment PM termination and creation of a new segment at F5 (VCC) level uni-directional ...
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F4 end-end PM flow F4 end-end PM flow F5 segment PM flow Terminate end-end or segment flow (PPMTEN + PPMTID) Originate end-end or segment flow (PPMOEN + PPMOID) Data collect end-end (PEDCEN + PEDCID) Data collect segment (PSDCID + PSDCEN) ...
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The AOP has one UTOPIA receive interface and one UTOPIA transmit interface with master capability at the PHY side and one receive and transmit interface with slave capability at the ATM side ( ). The interfaces are compliant to the ...
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Receive and transmit side of ATM and PHY side UTOPIA interface operate each from one clock which may be completely independent from the main chip clock SYSCLK. The UTOPIA clock frequency must be less than or equal to the main ...
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However, although 48 PHYs could be polled by this configuration only PHY are supported. 25.6 Mbit/s PHY0 25.6 Mbit/s Port 0..5 25.6 Mbit/s device 0 25.6 Mbit/s Adr 0..5 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s ...
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EN0 / CLAV0 0 EN1 / CLAV1 12 EN2 / CLAV2 do not connect EN3 / CLAV3 do not connect The poll cycle is identical in all modes, i.e. the address lines output all addresses from during ...
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The AOP uses external, synchronous, static RAM (SSRAM) for the storage of connection related OAM data. Two identical SSRAM interfaces are provided, one for each direction. The SSRAM chips are operated with the system clock MHz. ...
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U for upstream, D for downstream RAM SYSCLK Note that RCEx2 is unused and RCEx3 is used as additional address pin adr(15) when using 2 Mbit RAMs.The AOP uses 4-bursts to access the external RAMs. for the read ...
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SYSCLK ADSC ADV A(17: RDATx Input D1..D8 Dwords 1..8 from external RAM A1 Address from RMW Address Register A2 Address LCI2 from external RAM entry The AOP has a 16-bit microprocessor interface for control ...
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The interface is operating completely asynchronous to the system clock SysClk. This interface contains the boundary scan of all signal pins according to the standard [ ]. It consists of the pins shown in TCK TMS TDI TRST There are ...
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The following explanations applies for all Pins of a field in the table respectively: • Pins with a attached are connected with an internal pull up resistor. 1) • Pins with a attached are connected with an internal pull down ...
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Pin Definitions and Functions D12, B10, TXDATD C11, A10, (15:0) D10, B9, C10, A9, B8, A8, C9, B7, D8, A7, C8, B6 D13, A12, TXADRD B11, C12 (3:0) A11 TXPRTYD A15, C16, TXENBD B14, D15 (3:0) D7, A6, C7, TXCLAVD ...
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Pin Definitions and Functions AD18, AF19, TXDATU AE19, AF18, (15:0) AD17, AE18, AC17, AF17, AD16, AE17, AC15, AF16, AD15, AE16, AF15, AD14 AE23, AD21, TXADRU AF22, AE21 2) (3:0) AE15 TXPRTYU AD23, AE24, TXENBU AD22, AF23 1) (3:0) AD19, AF20, ...
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Pin Definitions and Functions L25, M24, RDATU L26, M23, (31:0) K25, L24, K26, K23, J25, K24, J26, H25, H26, J24, G25, H23, G26, H24, F25, G23, F26, G24, E25, E26, F24, D25, E23, D26, E24, C25, D24, C26 2) R25, ...
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Pin Definitions and Functions T3, U1, U4, RDATD V2, U3, V1, (31:0) W2, W1, V3, Y2, W4, Y1, W3, AA2, Y4, AA1, Y3, AB2, AB1, AC2, AB4, AC1, AB3, AD2, AC3, AD1, AF2, AE3, AF3, AE4, AD4, AF4 2) N2, ...
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Pin Definitions and Functions W25 FPCT2D V23 FPCT1D W26 FPCT2U W24 FPCT1U AF24 1) TDI AC14 1) TCK AD25 1) TMS AD26 1) TRST AE26 TDO Data Sheet O Cell Filter 2 detector output downstream. In case of match a ...
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Pin Definitions and Functions AC25 1) OUTTRI AC24 1) UTTRI Y23 2) STEST AB25 AOPIIDD AA24 NDTRO AB23, AB24, TSTBUSI AB26, AA25 AA26, Y25, TSTBUSO Y26, Y24 D6, D11, D16, D21, F4, F23, L4, L23, T4, T23, AA4, AA23, AC6, ...
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Ambient temperature under biasPXB Storage temperature IC supply voltage with respect to ground Voltage on any pin with respect to ground 1) ESD robustness HBM: 1 100 pF 1) According to MIL-Std 883D, method 3015.7 and ESD Association ...
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Boundary Scan Interface): Input low voltage Input high voltage Output low voltage Output high voltage(s) Average power supply current Average power up supply current (N SYSCLK cycles after reset) Average power dissipation Data Sheet –0.4 IL ...
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Input current Output leakage current Data Sheet -1 IIN 50 - 6-152 150 mA = for IN DD Inputs with internal Pull- Down resistor -200 mA = for IN SS Inputs with ...
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All inputs are driven to = 2.4 V for a logical 1 IH and to = 0.4 V for a logical 0 IL All outputs are measured ...
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MPADR 1 MPCS 2 MPWR 10 MPRDY MPDAT 1 MPADR setup time before MPCS low 2 MPCS setup time before MPWR low 3 MPRDY low delay after MPWR low 4 MPDAT setup time before MPWR high 5 Pulse width MPRDY ...
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MPADR 21 MPCS 22 MPRD 32 MPRDY MPDAT 21 MPADR setup time before MPCS low 22 MPCS setup time before MPRD low 23 MPRDY low delay after MPRD low 24 Pulse width MPRDY low 24 Pulse width MPRDY low (MPADR ...
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MPCS low to MPRDY low impedance 33 MPCS high to MPRDY high impedance For DMA operation the MPDREQ signal is necessary. It indicates that at least one more word is available within the AOP DMA buffer. When the microprocessor ...
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PH2 PH1 PH2 PH1 386EX:CLK2 T1 386EX:CLKOUT 386EX:RD 386EX:DRE 386EX:DACK +30ns RD output delay +40ns synchronisation in ASIC +20ns DRE output delay 40 Rising edge of MPDREQ after MPRD low 1 41 MPDREQ driven high before high impedance ...
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The AC characteristics of the UTOPIA Interface fulfill the standard of [1] and [2]. Setup and hold times of the 50 MHz UTOPIA Specification are valid. According to the UTOPIA Specification, the AC characteristics are based on the timing specification ...
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PHY devices, multiple output signals are multiplexed together). 90 signal going low impedance from clock Data Sheet 88 91 signal going low signal going high impedance to clock impedance from clock ...
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PHY (P) RXDATU(15:0) RXSOCU RXPRTYU RXCLAVU(3:0) RXENBU(3:0) RXADRU(3:0) UTPHYCLK TXDATD(15:0) TXSOCD TXPRTYD TXCLAVD(3:0) TXENBD(3:0) TXADRD(3:0) In the following tables (column DIR, Direction) defines a signal from the ATM Layer (transmitter, driver) to the PHY Layer (receiver ...
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All timings also apply to UTOPIA Level 1 8-bit data bus operation. The direction notification in the following tables apply to the UTOPIA master interface (AOP to PHY) 80 UTATMCLK TXDATU A<P [15:0], TXSOCU 85 TXPRTYU, ...
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UTPHYCLK TXDATD A>P [15:0], TXSOCD, 85 TXPRTYD, TXENBD[0] 86 TXCLAVD[0] A< UTATMCLK RXDATD A>P [15:0], 85 RXPRTYD 86 RXSOCD, A>P RXENBD[ RXCLAVD[0] A<P 89 Data Sheet PHY ...
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UTATMCLK TXDATU A<P [15:0], 85 TXSOCU, TXPRTYU 86 TXENBU A>P [3:0], 87 TXADRU [3:0] 86 TXCLAVU A<P [3: Data Sheet ATM Clk frequency (nominal) ATM Clk duty cycle ATM Clk ...
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UTPHYCLK RXENBU A>P [3:0], 85 RXADRU [3:0] 86 RXDATU A<P [15:0], 87 RXPRTYU RXSOCU, A<P RXCLAV 87 [3: Data Sheet PHY Clk frequency (nominal) PHY Clk ...
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UTPHYCLK TXDATD A>P [15:0], TXSOCD, 85 TXPRTYD, TXENBD [3:0], TXADRD [3:0] 86 TXCLAVD A<P [3: Data Sheet PHY Clk frequency (nominal) PHY Clk duty cycle PHY Clk peak-to-peak jitter PHY ...
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UTATMCLK RXENBD A>P [3:0] 85 RXADRD [3:0] 86 RXDATD A<P [15:0], 87 RXPRTYD RXSOCD, A<P RXCLAVD 87 [3: Data Sheet ATM Clk frequency (nominal) ATM Clk ...
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Timing of the Synchronous Static RAM Interfaces is simplified as all signals are referenced to the rising edge of SYSCLK. In PXB 4340 E AOP have identical delay times with reference to the clock. When reading from the RAM, the ...
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SYSCLK 130 FPCT2D, FPCT1D, FPCT2U, FPCT1U 130 Delay SYSCLK high to FPCT active 131 Delay SYSCLK high to FPCT inactive 4 132 FPCT high time in number of SYSCLK cycles Data Sheet 131 132 6-168 ns ...
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VDD CLK RESET 150 RESET pulse width 151 Number of SYSCLK cycles during RESET active Data Sheet 151 150 120 3 6-169 ns SYSCLK cycles 04.2000 ...
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TCK TMS TDI TDO TRST 160 : Period TCK TCK 160A : Frequency TCK TCK 161 TCK high time 162 TCK low time 163 Setup time TMS before TCK rising 164 Hold time TMS after TCK rising 165 Setup ...
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Input Capacitance Output Capacitance Load Capacitance at: UTOPIA Outputs MPDAT(15:0), MPRDY other outputs Airflow No airflow Airflow 200 lfpm = 1m/s Airflow 400 lfpm = 2m/s Airflow 600 lfpm = 3m/s Data Sheet 3 IN 2.5 OUT FO1 FO2 FO3 ...
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Ball Grid Array) Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet SMD = Surface Mounted Device 7-172 Dimensions in mm 04.2000 ...
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Junction to case Junction to ambient air without air flow Junction to ambient air with air flow 1.0 m/s Junction to ambient air with air flow 2.0 m/s Junction to ambient air with air flow 3.0 m/s Data Sheet 5 ...
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The following layer points are defined for both F4 and F5 OAM flows: • OEP = Originating End Point (end-to-end OAM cell flow) • TEP = Terminating End Point (end-to-end cell flow) • OSP = Originating Segment Point (segment cell ...
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OEP+OSP - OEP+OSP IP OEP+OSP OSP OEP+OSP TSP OEP+OSP OSP+TSP - TEP - TEP+TSP x: no meaning, Flows have to be adjusted bidirectionally -> in up- and downstream for each originating point in one direction the terminating point in the ...
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Data Sheet ...
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Data Sheet ...
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Data Sheet ...
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TMR1L(15:8) TMR2L(15:8) TMR3L(15:8) TMR4L(15:8) TMR5L(15:8) TMR6L(15:8) TMR7L(15:8) TMR8L(15:8) TMR9L(15:8) TMR10L(15:8) TMR11L(15:8) TMR12L(15:8) TMRxx = Registers for Insertion Buffer access 18 H Location ID #13 Location ID #9 Location ID #5 Location ID #1 Source ID #13 Source ID #9 Source ...
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H BEDC(15: BEDC(15:8) Data Sheet MCSN TUC (15:8) 0+1 BEDC(7:0) TUC (15: ...
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H BEDC(15: TRCC (15:8) 0+1 * TUC and TUC are copied from the received FM cell 0 0 TRCC ...
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TMR1L(15:8) TMR2L(15:8) TMR3L(15:8) TMR4L(15:8) TMR5L(15:8) TMR6L(15:8) TMR7L(15:8) TMR8L(15:8) TMR9L(15:8) TMR10L(15:8) TMR11L(15:8) TMR12L(15:8) TMRxx = Registers for Insertion Buffer access 80 H Data Sheet TMR1L(7:0) TMR2H(15:8) TMR2L(7:0) TMR3H(15:8) TMR3L(7:0) TMR4H(15:8) TMR4L(7:0) TMR5H(15:8) TMR5L(7:0) TMR6H(15:8) TMR6L(7:0) TMR7H(15:8) TMR7L(7:0) TMR8H(15:8) TMR8L(7:0) TMR9H(15:8) TMR9L(7:0) ...
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H Data Sheet xxxxxx : CRC-10(9:0) 8-183 04.2000 ...
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UTOPIA Level 1 Specification Version 2.01, March 21, 1994, ATM Forum 2. UTOPIA Level 2 Specification Version 1.0, June 1995, ATM Forum 3. IEEE 1596.3 Standard for Low-Voltage Differential Signals for SCI, Draft 1.3, Nov Joint Test ...
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OAM peration nd OEP riginating nd oint OSP riginating egment oint PM erformance PN ort umber PTI ayload ype ndication field of standardized ATM cell RDI emote efect ndication (I.610) SSRAM ynchronous tatic tbd o ...