RIVA128 STMicroelectronics, RIVA128 Datasheet
RIVA128
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RIVA128 Summary of contents
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DESCRIPTION The RIVA 128™ is the first 128-bit 3D Multimedia Accelerator to offer unparalleled 2D and 3D perfor- mance, meeting all the requirements of the main- stream PC graphics market and Microsoft’s PC’97. The RIVA 128 introduces the most ad- ...
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RIVA 128 1 REVISION HISTORY ...................................................................................................................... 1 RIVA 128 300PBGA DEVICE PINOUT .......................................................................................... 2 PIN DESCRIPTIONS ...................................................................................................................... 2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE ..................................................... 2.2 PCI 2.1 LOCAL BUS INTERFACE ........................................................................................ 2.3 SGRAM FRAMEBUFFER INTERFACE ................................................................................ 2.4 VIDEO PORT......................................................................................................................... 2.5 ...
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MULTIMEDIA ACCELERATOR 10 POWER-ON RESET CONFIGURATION........................................................................................ 11 DISPLAY INTERFACE ................................................................................................................... 11.1 PALETTE-DAC ...................................................................................................................... 11.2 PIXEL MODES SUPPORTED ............................................................................................... 11.3 HARDWARE CURSOR ......................................................................................................... 11.4 I2C INTERFACE.................................................................................................................... 11.5 ANALOG INTERFACE .......................................................................................................... 11.6 TV OUTPUT SUPPORT ........................................................................................................ 12 IN-CIRCUIT BOARD TESTING ...
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RIVA 128 1 REVISION HISTORY Date Section, page 15 Jul 97 6, page 28 Update of SGRAM framebuffer interface configuration diagrams. 28 Aug 97 13.5, page 59 Change of DAC specification from 206MHz to 230MHz max. operating frequency. 29 Aug ...
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MULTIMEDIA ACCELERATOR 1 RIVA 128 300PBGA DEVICE PINOUT NOTES 1 NIC = No Internal Connection. Do not connect to these pins. 2 VDD=3.3V Signals denoted with an asterisk are defined for future expansion. See Pin Descriptions , Section ...
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RIVA 128 2 PIN DESCRIPTIONS 2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE Signal I/O Description AGPST[2:0] I AGP status bus providing information from the arbiter to the RIVA 128 on what it may do. AGPST[2:0] only have meaning to the RIVA ...
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MULTIMEDIA ACCELERATOR Signal I/O Description PCICBE[3:0]# I/O Multiplexed bus command and byte enable signals. During the address phase of a trans- action PCICBE[3:0]# define the bus command, during the data phase PCICBE[3:0]# are used as byte enables. The ...
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RIVA 128 Signal I/O Description PCIGNT# I Grant. This signal indicates to the RIVA 128 that access to the bus has been granted and it can now become bus master. When connected to AGP additional information is provided on AGPST[2:0] ...
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MULTIMEDIA ACCELERATOR 2.5 DEVICE ENABLE SIGNALS Signal I/O Description ROMCS# O Enables reads from an external 64Kx 8 or 32Kx8 ROM or Flash ROM. This signal is used in conjunction with framebuffer data lines as described above in ...
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RIVA 128 2.9 TEST Signal I/O Description TESTMODE I For designs which will be tested in-circuit, this pin should be connected to GND through a 10K TESTMODE is asserted, MP_AD[3:0] are reassigned as TESTCTL[3:0] respectively. Information on in-circuit test is ...
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MULTIMEDIA ACCELERATOR 3 OVERVIEW OF THE RIVA 128 The RIVA 128 is the first 128-bit 3D Multimedia Accelerator to offer unparalleled 2D and 3D perfor- mance, meeting all the requirements of the main- stream PC graphics market and ...
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RIVA 128 3.3 2D ACCELERATION The RIVA 128's 2D rendering engine delivers in- dustry-leading Windows acceleration mance: 100MHz 128-bit graphics engine optimized for single cycle operation into the 128-bit SGRAM interface supporting up to 1.6GBytes/s Acceleration functions optimized for minimal ...
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MULTIMEDIA ACCELERATOR Per-pixel color keying Multiple video windows with hardware color space conversion and filtering Planar YUV12 (4:2:0) to/from packed (4:2:2) conversion for software MPEG acceleration and H.261 video conferencing applications Accelerated playback of industry standard co- decs ...
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RIVA 128 3.10 CUSTOMER EVALUATION KIT A Customer Evaluation Kit (CEK) is available for evaluating the RIVA 128. The CEK includes a PCI or AGP adapter card designed to support the RIVA 128 feature set, an evaluation CD-ROM contain- ing ...
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MULTIMEDIA ACCELERATOR 4 ACCELERATED GRAPHICS PORT (AGP) INTERFACE The Accelerated Graphics Port (AGP high performance, component level interconnect targeted at 3D graphical display applications and based on performance enhancements to the PCI local bus. Figure 1. ...
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RIVA 128 the AGP bridge chip and RIVA 128 are the only devices on the AGP bus - all other I/O devices re- main on the PCI bus. The add-in slot defined for AGP uses a new con- nector body ...
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MULTIMEDIA ACCELERATOR Figure 3. Basic PCI transaction on AGP 1 PCICLK PCIFRAME# PCIAD[31:0] PCICBE[3:0]# PCIIRDY# PCITRDY# PCIDEVSEL# PCIREQ# PCIGNT# xxx 111 AGPST[2:0] An example of a PCI transaction occurring between an AGP command cycle and return of data ...
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RIVA 128 Figure 5. Basic AGP pipeline concept Bus Idle Pipelined data transfer Intervene A1 cycles Pipeline operation Memory access pipelining provides the main per- formance enhancement of AGP over PCI. AGP pipelined bus transactions share most of the PCI ...
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MULTIMEDIA ACCELERATOR Figure 6. Single address - no delay by master 1 2 PCICLK AGPPIPE# PCIAD[31:0] PCICBE[3:0]# PCIREQ# PCIGNT# xxx 111 AGPST[2:0] Figure 7 shows the RIVA 128 enqueuing 4 requests, where the first request is delayed by ...
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RIVA 128 AGP timing specification Figure 8. AGP clock specification 0.6VDD 0.5VDD PCICLK 0.4VDD 0.3VDD Table 1. AGP clock timing parameters Symbol t PCICLK period CYC t PCICLK high time HIGH t PCICLK low time LOW PCICLK slew rate NOTES ...
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MULTIMEDIA ACCELERATOR 5 PCI 2.1 LOCAL BUS INTERFACE 5.1 RIVA 128 PCI INTERFACE The RIVA 128 supports a glueless interface to PCI 2.1 with both master and slave capabilities. The host interface is fully compliant with the 32-bit ...
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RIVA 128 5.2 PCI TIMING SPECIFICATION The timing specification of the PCI interface takes the form of generic setup, hold and delay times of tran- sitions to and from the rising edge of PCICLK as shown in Figure 11. Figure ...
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MULTIMEDIA ACCELERATOR Figure 12. PCI Target write - PCICLK PCIAD[31:0] address PCICBE[3:0]# bus cmd PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# Figure 13. PCI Target write - Slave Write (multiple 32-bit with zero wait state DEVSEL# response) PCICLK PCIAD[31:0] address PCICBE[3:0]# ...
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RIVA 128 Figure 14. PCI Target read - Slave Read (1-cycle single word read) PCICLK PCIAD[31:0] PCICBE[3:0]# bus cmd PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# Figure 15. PCI Target read - Slave Read (slow single word read) PCICLK PCIAD[31:0] address PCICBE[3:0]# bus ...
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MULTIMEDIA ACCELERATOR Figure 16. PCI Master write - multiple word PCICLK PCIREQ# PCIGNT# PCIAD[31:0] PCICBE[3:0]# bus cmd PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# Figure 17. PCI Master read - multiple word PCICLK PCIREQ# PCIGNT# PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# ...
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RIVA 128 Figure 18. PCI Target configuration cycle - Slave Configuration Write PCICLK AD[31:0] address PCICBE[3:0]# bus cmd PCIFRAME# PCIIDSEL PCIIRDY# PCITRDY# PCIDEVSEL# Figure 19. PCI Target configuration cycle - Slave Configuration Read PCICLK PCIAD[31:0] address PCICBE[3:0]# bus cmd PCIFRAME# ...
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MULTIMEDIA ACCELERATOR Figure 20. PCI basic arbitration cycle PCICLK PCIREQ#_a PCIREQ#_b PCIGNT#_a PCIGNT#_b PCIFRAME# PCIAD[31:0] Figure 21. Target initiated termination PCICLK 1 PCIFRAME# PCIIRDY# PCITRDY# PCISTOP# PCIDEVSEL# PCICLK 1 PCIFRAME# PCIIRDY# PCITRDY# PCIPCISTOP# PCIDEVSEL# address data access A ...
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RIVA 128 6 SGRAM FRAMEBUFFER INTERFACE The RIVA 128 SGRAM interface can be configured with a 2MByte 64-bit or 4MByte 128-bit data bus. With a 128-bit bus, 4MBytes of SGRAM is supported as shown in Figure 22. All of the ...
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MULTIMEDIA ACCELERATOR Figure 23. 2 and 4MByte SGRAM configurations FBDQM[0]# FBDQM[1]# FBDQM[2]# FBDQM[3]# FBCS[0]# FBCLK0 FBDQM[4]# FBDQM[5]# FBDQM[6]# FBDQM[7]# FBCS[0]# FBCLK1 FBD[127:0] NOTE 1 RIVA 128 has a pin reserved for an eleventh address signal, FBA[10], which may ...
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RIVA 128 Table 5. Truth table of supported SGRAM commands 1 Command FBCSx Command inhibit (NOP) No operation (NOP) Active (select bank and activate row) Read (select bank and column and start read burst) Write (select bank and column and ...
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MULTIMEDIA ACCELERATOR 6.3 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of SGRAM to give reduced clock skew and loading. Additionally there is a clock feedback loop between FBCLK2 and ...
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RIVA 128 Symbol Parameter t CLK low time CL t Address setup time AS t Address hold time AH t Write data setup time DS t Write data hold time DH t Read data hold time OH t Read data ...
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MULTIMEDIA ACCELERATOR Figure 28. SGRAM read to write, read latency of three FBCLKx TDDQM Command FBA[9:0] bank, col n FBD[63:0] Table 7. SGRAM I/O timing parameters Symbol Parameter t Data out high impedance time HZ t Write data ...
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RIVA 128 Figure 31. SGRAM read to precharge, read latency of two FBCLKx Command FBA[9:0] FBD[63:0] NOTE 1 FBDQM is active (low) Figure 32. SGRAM read to precharge, read latency of three FBCLKx Command FBA[9:0] FBD[63:0] NOTE 1 FBDQM is ...
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MULTIMEDIA ACCELERATOR Figure 34. SGRAM Active to Read or Write FBCLKx active Command Table 8. SGRAM timing parameters Symbol Parameter t FBCSx, FBRAS#, FBCAS#, FBWE#, CS FBDQM setup time t FBCSx, FBRAS#, FBCAS#, FBWE#, CH FBDQM hold time ...
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RIVA 128 7 VIDEO PLAYBACK ARCHITECTURE The RIVA 128 video playback architecture is de- signed to allow playback of CCIR PAL or NTSC video formats with the highest quality while requir- ing the smallest video surface. The implementa- tion is ...
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MULTIMEDIA ACCELERATOR 7.1 VIDEO SCALER PIPELINE The RIVA 128 video scaler pipeline performs stretching of video images in any arbitrary factor in both horizontal and vertical directions. The video scaler pipeline consists of the following stages: 1 Vertical ...
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RIVA 128 Figure 36. Displaying 2 fields with 1:1 ratio Frame 1 (Top field) Line 11 Interpolated line (Line 11 & 13) Line 13 The RIVA 128 video overlay handles interlaced vid displaying every field, at the original ...
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MULTIMEDIA ACCELERATOR 8 VIDEO PORT The RIVA 128 Multimedia Accelerator introduces a multi-function Video Port that has been designed to exploit the bus mastering functionality of the RIVA 128. The Video Port is compliant with a sim- plified ...
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RIVA 128 8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC The Media Port transfers data using a Polling Pro- tocol. The Media Port is enabled on the RIVA 128 by the host system software. The first cycle after being enabled ...
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MULTIMEDIA ACCELERATOR 8.3 TIMING DIAGRAMS Figure 38. Poll cycle MPCLK MPFRAME# ] MP_AD[7:0 A0 MPDTACK# Figure 39. Poll cycle throttled by slave MPCLK MPFRAME# ] MP_AD[7:0 A0 MPDTACK# Figure 40. CPU write cycle MPCLK MPFRAME# ] MP_AD[7:0 A0 ...
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RIVA 128 Figure 42. CPU read issue cycle - cannot be throttled by slave MPCLK MPFRAME# ] MP_AD[7:0 A0 Figure 43. CPU read_receive cycle MPCLK MPFRAME# ] MP_AD[7:0 A0 MPDTACK# Figure 44. CPU read_receive cycle - throttled by slave MPCLK ...
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MULTIMEDIA ACCELERATOR Figure 46. CD write cycle - terminated by slave in middle of transfer MPCLK MPFRAME# MP_AD[7:0] A0 MPDTACK# MPSTOP# Figure 47. CD write cycle - terminated by slave on byte 31 MPCLK MPFRAME# MP_AD[7:0] A0 MPDTACK# ...
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RIVA 128 Figure 50. UCD read cycle, terminated by slave, throttled by slave MPCLK MPFRAME# MP_AD[7:0] A0 MPDTACK# MPSTOP# Figure 51. UCD read cycle, slave termination after MPFRAME# deasserted, data taken MPCLK MPFRAME# MP_AD[7:0] A0 MPDTACK# MPSTOP# Figure 52. UCD ...
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MULTIMEDIA ACCELERATOR 8.4 656 MASTER MODE Table 11 shows the Video Port pin definition when the RIVA 128 is configured in ITU-R-656 Master Mode. Before entering this mode, RIVA 128 dis- ables all Video Port devices so that ...
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RIVA 128 8.5 VBI HANDLING IN THE VIDEO PORT RIVA 128 supports two basic modes for VBI data capture. VBI mode 1 is for use with the Philips SAA7111A digitizer, VBI mode 2 is for use with the Samsung KS0127 ...
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MULTIMEDIA ACCELERATOR 9 BOOT ROM INTERFACE BIOS and initialization code for the RIVA 128 is accessed from a 32KByte ROM. The RIVA 128 memory bus interface signals FBD[15:0] and FBD[31:24] are used to address and access one of ...
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RIVA 128 Table 14. ROM interface timing parameters Symbol Parameter t ROMCS# active pulse width BRCS t ROMCS# precharge time BRCA t Read valid to ROMCS# active BRV Read hold from ROMCS# inactive t BRH t Address setup to ROMCS# ...
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MULTIMEDIA ACCELERATOR 10 POWER-ON RESET CONFIGURATION The RIVA 128 latches its configuration on the trail- ing edge of RST# and holds its system bus inter- face in a high impedance state until this time. To accomplish this, pull-up ...
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RIVA 128 The following example configuration is shown in Figure 57: Subsystem Vendor ID initialized to 0 and writeable by system BIOS (see Appendix A, page 70) 8Mbit 128K x 2 bank x 32 SGRAM 128-bit framebuffer interface AGP including ...
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MULTIMEDIA ACCELERATOR 11 DISPLAY INTERFACE 11.1 PALETTE-DAC The Palette-DAC integrated into the RIVA 128 supports a traditional pixel pipeline with the follow- ing enhancements: Support for 10:10:10, 8:8:8, 5:6:5 and 5:5:5 di- rect color pixel modes Support for ...
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RIVA 128 mode pixel format, the least significant bits of each color are located separately in the top byte of the pixel. This also permits an 8:8:8 mode without gamma with <1% error if desired ...
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MULTIMEDIA ACCELERATOR 11.4 SERIAL INTERFACE The RIVA 128 serial interface supports connection to DDC1/2B, DDC2AB and DDC2B+ compliant monitors and to serial interface controlled video decoders and tuners. Supported video decoder chips include Philips SAA7110, SAA7111A, ITT 3225 ...
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RIVA 128 11.5 ANALOG INTERFACE Figure 58. Recommended circuit (crystal circuit is for designs not supporting TV out) Local PLLVDD plane These components should be placed as close to the RIVA 128 outputs as ...
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MULTIMEDIA ACCELERATOR 11.6 TV OUTPUT SUPPORT Reference clock options The RIVA 128 supports two synthesizer reference clock frequencies; 13.5MHz and 14.31818MHz. The reference clock frequency is determined by a crystal or reference clock connected to the XTA- LIN ...
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RIVA 128 Figure 60. Interface to monitor or television TV RGB Encoder R RIVA 128 G B Monitor detection Figure 60 shows the typical connection of a televi- sion or computer monitor to the RIVA 128s’ DAC outputs. The RIVA ...
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MULTIMEDIA ACCELERATOR 12 IN-CIRCUIT BOARD TESTING The RIVA 128 has a number of features designed to support in-circuit board testing. These include: Dedicated test mode input and dual-function test mode select pins selecting the following modes: - Pin ...
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RIVA 128 13 ELECTRICAL SPECIFICATIONS 13.1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter VDD/AVDD DC supply voltage Voltage on input and output pins TS Storage temperature (ambient) TA Temperature under bias Analog output current (per output) DC digital output current (per output) ...
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MULTIMEDIA ACCELERATOR Symbol Parameter VIL Input logic 0 voltage VOH Output logic 1 level VOL Output logic 0 level IOH Output load current, logic 1 level IOL Output load current, logic 0 level NOTE 1 Tested but not ...
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RIVA 128 NOTES 1 Blanking pedestals are not supported in TV output mode. 2 VREF = 1.235V, RSET = 147 3 LSB = 1 LSB of 8-bit resolution DAC 8 4 About the midpoint of the distribution of the three ...
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MULTIMEDIA ACCELERATOR 14 PACKAGE DIMENSION SPECIFICATION 14.1 300 PIN BALL GRID ARRAY PACKAGE Figure 61. RIVA 128 300 Plastic Ball Grid Array Package dimension reference D2 Pin 1 indicator 0.300 0.100 SOLDER BALL (Typ) Table 21. RIVA 128 ...
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RIVA 128 15 REFERENCES 1 RIVA 128 Turnkey Manufacturing Package TMP, Design Guide , NVIDIA Corp./SGS-THOMSON Micro- electronics 2 RIVA 128 Programming Reference Manual, NVIDIA Corp./SGS-THOMSON Microelectronics 3 Accelerated Graphics Port Interface Specification, Revision 1.0 , Intel Corporation , July ...
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MULTIMEDIA ACCELERATOR APPENDIX Descriptions of register contents include an indication if register fields are readable (R) or writable (W) and the initial power-on or reset value of the field (I) . ‘-’ indicates not readable / writable, X ...
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RIVA 128 Byte offsets 0x07 - 0x04 0x07 Device Status Register (0x07 - 0x06) Bits Function 31 Reserved ...
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MULTIMEDIA ACCELERATOR Bits Function SERR_ENABLE is an enable bit for the SERR# driver. 8 0=Disables the SERR# driver 1=Enables the SERR# driver 7:6 Reserved 5 PALETTE_SNOOP indicates that VGA compatible devices should snoop their palette registers. 0=Palette accesses ...
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RIVA 128 Byte offsets 0x0B - 0x08 0x0B Class Code Register (0x0B - 0x09) Bits Function 31:8 The ...
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MULTIMEDIA ACCELERATOR Byte offsets 0x0F - 0x0C 0x0F Bits Function 31:24 Reserved 23:16 HEADER_TYPE identifies the ...
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RIVA 128 Byte offsets 0x13 - 0x10 0x13 Base Memory Address Register (0x13 - 0x10) Bits Function 31:24 ...
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MULTIMEDIA ACCELERATOR Byte offsets 0x17 - 0x14 0x17 Base Memory Address Register (0x17 - 0x14) Bits ...
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RIVA 128 Byte offsets 0x2F - 0x2C 0x2F Subsystem Vendor ID (0x2F - 0x2C) Bits Function 31:16 SUBSYSTEM_ID ...
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MULTIMEDIA ACCELERATOR Byte offsets 0x33 - 0x30 0x33 Expansion ROM Base Address Register (0x33 - 0x30) ...
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RIVA 128 Byte offsets 0x37 - 0x34 0x37 Capabilities Pointer Register (0x37 - 0x34) Bits Function 31:8 Reserved ...
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MULTIMEDIA ACCELERATOR Byte offset 0x3F - 0x3C 0x3F MAX_LAT Register (0x3F ) Bits Function 31:24 The ...
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RIVA 128 Byte offsets 0x43 - 0x40 0x43 Writeable Subsystem Vendor ID (0x43 - 0x40) Bits Function 31:16 ...
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MULTIMEDIA ACCELERATOR Byte offsets 0x4B - 0x48 AGP Status Register (0x4B - 0x48 = CAP_PTR+4) ...
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RIVA 128 Byte offsets 0x4F - 0x4C AGP Command Register (0x4F - 0x4C = CAP_PTR + 8) ...
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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from ...