AM28F020-150JC Advanced Micro Devices, AM28F020-150JC Datasheet

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AM28F020-150JC

Manufacturer Part Number
AM28F020-150JC
Description
2 megabit CMOS 12.0 volt, bulk erase flash memory
Manufacturer
Advanced Micro Devices
Datasheet

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Am28F020
2 Megabit (256 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The Am28F020 is a 2 Megabit Flash memory orga-
nized as 256 Kbytes of 8 bits each. AMD’s Flash mem-
ories offer the most cost-effective and reliable read/
write non-volatile random access memor y. The
Am28F020 is packaged in 32-pin PDIP, PLCC, and
TSOP versions. It is designed to be reprogrammed and
erased in-system or in standard EPROM programmers.
Th e Am 28F 020 i s eras ed w hen s h ip ped from
the factory.
The standard Am28F020 offers access times of as fast
as 70 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten-
tion, the device has separate chip enable (CE#) and
output enable (OE#) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F020 uses a command register to manage this
functionality, while maintaining a JEDEC-standard 32-
pin pinout. The command register allows for 100% TTL
level control inputs and fixed power supply levels during
erase and programming, while maintaining maximum
EPROM compatibility.
AMD’s Flash technology reliably stores memory con-
tents even after 10,000 erase and program cycles. The
AMD cell is designed to optimize the erase and pro-
Publication# 14727
Issue Date: January 1998
High performance
— Access times as fast as 70 ns
CMOS low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
Compatible with JEDEC-standard byte-wide
32-pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
10,000 write/erase cycles minimum
Write and erase voltage 12.0 V 5%
FINAL
Rev: F Amendment/+2
gramming mechanisms. In addition, the combination of
advanced tunnel oxide processing and low internal
electric fields for erase and programming operations
produces reliable cycling. The Am28F020 uses a
12.0 5% V
and Flashrite functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 mA on
address and data pins from –1 V to V
The Am28F020 is byte programmable using 10 µs
programming pulses in accordance with AMD’s
temperature programming time of the Am28F020 is
four seconds. The entire chip is bulk erased using 10
ms erase pulses according to AMD’s Flasherase
accomplished in less than one second. The windowed
package and the 15–20 minutes required for EPROM
erasure using ultraviolet light are eliminated.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine, which
controls the erase and programming circuitry. During
write cycles, the command register internally latches
Flashrite programming algorithm. The typical room
algorithm. Typical erasure at room temperature is
Latch-up protected to 100 mA from
–1 V to V
Flasherase Electrical Bulk Chip Erase
— One second typical chip erase time
Flashrite Programming
— 10 µs typical byte program time
— 4 s typical chip program time
Command register architecture for
microprocessor/microcontroller compatible
write interface
On-chip address and data latches
Advanced CMOS flash memory technology
— Low cost single transistor memory cell
Automatic write/erase pulse stop timer
PP
CC
supply input to perform the Flasherase
+1 V
CC
+1 V.

Related parts for AM28F020-150JC

AM28F020-150JC Summary of contents

Page 1

... TSOP 10,000 write/erase cycles minimum Write and erase voltage 12 GENERAL DESCRIPTION The Am28F020 Megabit Flash memory orga- nized as 256 Kbytes of 8 bits each. AMD’s Flash mem- ories offer the most cost-effective and reliable read/ write non-volatile random access memor y. The Am28F020 is packaged in 32-pin PDIP, PLCC, and TSOP versions ...

Page 2

... For system design simplification, the Am28F020 is designed to support either WE# or CE# controlled w rites. During a system write cycle, addresses are latched on the falling edge of WE# or CE#, whichever occurs last. Data is latched on the rising edge of WE# or CE#, whichever occurs first ...

Page 3

... A15 3 30 A17 A12 4 29 A14 A7 A13 A11 A10 DQ7 A0 DQ0 DQ6 13 20 DQ1 DQ5 14 19 DQ2 15 DQ4 18 V DQ3 14727F-2 Note: Pin 1 is marked for orientation DQ0 Am28F020 PLCC A14 29 6 A13 A11 10 24 OE# (G#) 11 A10 23 12 CE# (E DQ7 14727F-3 3 ...

Page 4

... CONNECTION DIAGRAMS (continued) A11 A13 4 A14 5 A17 A16 10 A15 11 A12 A10 LOGIC SYMBOL 4 TSOP 32-Pin TSOP—Standard Pinout 32-Pin TSOP—Reverse Pinout 18 A0–A17 DQ0–DQ7 # CE (E) OE# (G#) WE# (W#) Am28F020 # A10 A11 A13 28 A14 27 A17 A16 22 A15 21 A12 14727F-4 8 14727F-5 ...

Page 5

... AM28F020 -70 J DEVICE NUMBER/DESCRIPTION Am28F020 2 Megabit (256 K x 8-Bit) CMOS Flash Memory Valid Combinations AM28F020-70 AM28F020-90 AM28F020-120 AM28F020-150 AM28F020-200 C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0°C to +70° Industrial (– ...

Page 6

... Write Enable active low input controls the write function of the command register to the memory array. The target address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writing to the device. Am28F020 5% or 10%) must be at high voltage in ...

Page 7

... The device also incorporates several features to pre- vent inadvertent write cycles resulting fromV up and power-down transitions or system noise. Low V Write Inhibit CC To avoid initiation of a write cycle during V and power-down, the device locks out write cycles for Am28F020 power- CC power- ...

Page 8

... CC LKO Write Pulse “Glitch” Protection Noise pulses of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle. FUNCTIONAL DESCRIPTION Description of User Modes Table 1. Am28F020 Device Bus Operations Operation Read Standby Output Disable Read-Only Auto-Select Manufacturer Code (Note 2) ...

Page 9

... For the device these two bytes are given in Table 2 of the device data sheet. All identifiers for manufac- turer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit. Table 2. Am28F020 Auto Select Code Am28F020 (11 13 address A9. Two ID ...

Page 10

... In order to write, OE# must and CE# and WE# IH must any pin is not in the correct state a write IL command will not be executed. Table 3. Am28F020 Command Definitions Operation Command (Note 4) Read Memory Read Auto select Erase Setup/Erase Write Erase-Verify Program Setup/Program ...

Page 11

... Program Setup) to the command register. Figure 1 and Table 4, the Flasherase electrical erase algorithm, illustrate how commands and bus operations are combined to per- form electrical erasure. Refer to AC Erase Characteris- tics and Waveforms for specific timing parameters. Am28F020 11 ...

Page 12

... Write Erase Setup Command Write Erase Command Time out 10 ms Write Erase Verify Time out 6 µs Read Data from Device No Increment Data = FFh PLSCNT Yes No Last Address Yes Write Reset Command Apply V PPL Erasure Completed Flasherase Electrical Erase Algorithm Am28F020 Increment Address 11559G-6 ...

Page 13

... Data = FFh, reset the register for read operations Wait for V PP parameters. The V power supply can be hard-wired to the device may be ground, no connect with a resistor tied to ground, or less than V PPL Am28F020 pin. Figure 1 illustrates the electrical PP Comments Ramp to V (Note 1) PPH ) WHWH2 ...

Page 14

... This command terminates the erase oper- ation on the rising edge of the WE# pulse (section D). The Erase-verify command also stages the device for data verification (section F). After each erase operation each byte must be verified. The byte address to be verified must be supplied with Am28F020 Data Out ...

Page 15

... Most bytes verify after the first or second pulse. The entire sequence of pro- gramming and byte verification is performed with high voltage applied to the V PP lustrate the programming algorithm. Am28F020 pin. Figure 3 and Table 5 il- 15 ...

Page 16

... Write Program Command (A/D) Time out 10 µs Write Program Verify Command Time out 6 µs Read Data from Device No Verify Byte Increment PLSCNT Yes No Last Address Yes Write Reset Command Apply V PPL Programming Completed Flashrite Programming Algorithm Am28F020 No PLSCNT = 25? Yes Apply V PPL Device Failed 11559G-8 ...

Page 17

... Compare Data Output to Data Expected Data = FFh, resets the register for read operations. Wait for V PP parameters. The V power supply can be hard-wired to the device may be ground, no connect with a resistor tied to ground, or less than V PPL Am28F020 Comments Ramp to V (Note 1) PPH ) WHWH1 Ramp to V (Note 1) PPL + 2 ...

Page 18

... Upon completion of the program timing routine, the mi- croprocessor must write the program-verify command (C0h). This command terminates the programming op- eration on the rising edge of the WE# pulse (section D). The program-verify command also stages the device for data verification (section F). Another software timing Am28F020 Data Out ...

Page 19

... Programming In-System Flash memories can be programmed in-system standard PROM programmer. The device may be sol- dered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board. Am28F020 CC and ...

Page 20

... The operation is initiated by writing 80h or 90h into the command register. Following this command, a read cycle address 0000h retrieves the manufacturer code of 01h. A read cycle from address 0001h returns the device code. To terminate the operation necessary to write another valid command, such as Reset (FFh), into the register. Am28F020 ...

Page 21

... V to +5. Voltages PP to Read . . . . . . . . . . . . . . . . . . . . . . . . –0 +12 Program, Erase, and Verify . . . . . . +11 +12.6 V +2.0 V for periods Operating ranges define those limits between which the CC functionality of the device is guaranteed. is –0 may overshoot PP Am28F020 ). . . . . . . . . . . .0°C to +70° .–40°C to +85° .–55°C to +125° ...

Page 22

... MAXIMUM OVERSHOOT Maximum Negative Input Overshoot +0.8 V –0.5 V –2.0 V Maximum Positive Input Overshoot 0 2.0 V Maximum V Overshoot PP 14 Am28F020 14727F-10 14727F-11 14727F-12 ...

Page 23

... PP V PPH Operations V Low V Lock-out Voltage LKO CC Notes: 1. Caution: The Am28F020 must not be removed from (or inserted into) a socket when V the voltage difference between V PP time specification of 500 ns minimum tested with OE simulate open outputs. CC1 IH 3. Maximum active power usage is the sum ...

Page 24

... Read/Write PP V PPH Operations V Low V Lock-out Voltage LKO CC Notes: 1. Caution: The Am28F020 must not be removed from (or inserted into) a socket when V the voltage difference between V PP time specification of 500 ns minimum tested with simulate open outputs. CC1 IH 3. Maximum active power usage is the sum ...

Page 25

... Figure 5. Am28F020—Average I TEST CONDITIONS Device Under Test C L 6.2 k Note: Diodes are IN3064 or equivalent Figure 6. Test Setup Frequency in MHz Active vs. Frequency CC VCC = 5.5 V, Addressing Pattern = Minmax Data Pattern = Checkerboard 5.0 V Test Condition 2.7 k Output Load Output Load Capacitance, C (including jig capacitance) ...

Page 26

... V for a logic “0”. Input pulse rise and fall times are 10 ns. -70 Min 70 Max 70 Max 70 Max 35 Min 0 Max 20 Min 0 Max 20 Min 0 Min 6 Min 50 Am28F020 Test Points 1.5 V Input Output 14727F-15 Am28F020 Speed Options -90 -120 -150 -200 90 120 150 200 90 120 150 200 90 120 150 200 ...

Page 27

... Chip Enable-Controlled Writes: Write operations are driven by the valid combination of Chip Enable (CE#) and Write Enable (WE#). In systems where CE# defines the Write Pulse Width (within a longer WE# timing waveform) all setup, hold and inactive WE# times should be measured relative to the CE# waveform. 4. Not 100% tested. Am28F020 Speed Options -70 -90 Min ...

Page 28

... Changing from Does Not Apply Center Line is High Impedance State (High Z) Device and Outputs Data Enabled Valid Addresses Stable AVAV GLQV ELQV GLQX OLZ ELQX LZ Output Valid AVQV ACC Am28F020 OUTPUTS Changing, State Unknown Standby, Power-Down t EHQZ ( GHQZ ( AXQX OH High Z 14727F-14 ...

Page 29

... PP V PPL Figure 8. Erase Erase-Verify Command Erasure Command AVWL WHEH CH t WHWH2 GHWL OES WHWL WPH WHDX DH DATA IN DATA IN = 20h = 20h AC Waveforms for Erase Operations Am28F020 Erase Standby, Verification Power-down AVAV WLAX EHQZ DF t WHGL GHQZ GLQV GLQX OLZ AXQX OH VALID ...

Page 30

... Figure 9. AC Waveforms for Programming 30 Program Command Latch Address Programming and Data Command WLAX WHEH CH t WHWH1 GHWL OES WHWL WPH WHDX DH DATA IN DATA IN = 40h Am28F020 Programming Standby, Verify Verification Power-down AVAV GHQZ DF t WHGL GHQZ GLQV GLQX AXQX OH VALID DATA IN DATA ...

Page 31

... Excludes 00h programming prior to erasure 4 25 sec Excludes system-level overhead Cycles Parameter = 5.0 V, one pin at a time. CC Test Conditions OUT 25° 1.0 MHz. A Test Conditions 150 C 125 C Am28F020 Comments Min Max ) –1 –1 1 –100 mA +100 mA Typ Max Unit Min Unit ...

Page 32

... SEATING PLANE .015 .016 .060 .022 .009 .015 .125 .140 .080 .095 SEATING PLANE .013 .021 .050 REF. Am28F020 .600 .625 .009 .015 .630 .700 0 10 16-038-S_AG PD 032 EC75 5-28-97 lv .042 .056 .400 REF. .490 .530 16-038FPO-5 PL 032 ...

Page 33

... PHYSICAL DIMENSIONS TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 1 1.20 MAX 33 18.30 18.50 19.80 20. Am28F020 0.95 1.05 7.90 8.10 0.50 BSC 0.05 0.15 0.08 16-038-TSOP-2 0.20 TS 032 DA95 0.10 3-25-97 lv 0.21 0.50 0.70 ...

Page 34

... PHYSICAL DIMENSIONS TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 1 1.20 MAX 18.30 18.50 19.80 20. 0.50 0.70 Am28F020 0.95 1.05 7.90 8.10 0.50 BSC 0.05 0.15 16-038-TSOP-2 0.08 TSR032 0.20 DA95 0.10 3-25-97 lv 0.21 34 ...

Page 35

... Verify Command box. This is a correction to the diagram on page 6-189 of the 1998 Flash Memory Data Book. Revision F+2 Programming In A PROM Programmer: Deleted the paragraph “(Refer to the AUTO SELECT paragraph in the ERASE, PROGRAM, and READ MODE section for programming the Flash memory de- vice in-system).” Am28F020 ...

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