ADSP-21266SKBCZ-2B Analog Devices Inc, ADSP-21266SKBCZ-2B Datasheet - Page 12

• Manufacturer Part Number: ADSP-21266SKBCZ-2B
• Manufacturer: Analog Devices Inc

Specifications of ADSP-21266SKBCZ-2B

• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Lead Free Status / Rohs Status: Compliant

ADSP-21261/ADSP-21262/ADSP-21266
Table 6. Pin Descriptions (Continued)
1
2
3
4
Pin
CLK_CFG1–0
RESETOUT
RESET
TCK
TMS
TDI
TDO
TRST
EMU
V
V
A
A
GND
RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.
Output only is a three-state driver with its output path always enabled.
Input only is a three-state driver, with both output path and pull-up disabled.
Three-state is a three-state driver, with pull-up disabled.
DDINT
DDEXT
VDD
VSS
Type
I
O
I/A
I
I/S
I/S
O
I/A
O (O/D)
P
P
P
G
G
State During and
After Reset
Input only
Output only
Input only
Input only
Three-state with
pull-up enabled
Three-state with
pull-up enabled
Three-state
Three-state with
pull-up enabled
Three-state with
pull-up enabled
3
4
Rev. F | Page 12 of 44 | July 2009
Function
Core/CLKIN Ratio Control. These pins set the start up clock frequency. See
description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
Reset Out. Drives out the core reset signal to an external device.
Processor Reset. Resets the ADSP-2126x to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed
low) after power-up or held low for proper operation of the ADSP-2126x.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a
22.5 k internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5
k internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the ADSP-2126x. TRST has a 22.5 k internal
pull-up resistor.
Emulation Status. Must be connected to the ADSP-2126x Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a
22.5 k internal pull-up resistor.
Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor
(13 pins on the BGA package, 32 pins on the LQFP package).
I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the LQFP
package).
Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL (clock
generator). This pin has the same specifications as V
circuitry is required.
Analog Power Supply Return.
Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).
For more information, see Power Supplies on Page 7.
DDINT
, except that added filtering
Table 9
for a