CY8C5568AXI-060 Cypress Semiconductor Corp, CY8C5568AXI-060 Datasheet - Page 21

• Manufacturer Part Number: CY8C5568AXI-060
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5568AXI-060

• Lead Free Status / Rohs Status: Compliant

generated) may be routed directly to the eight digital clock
dividers. This is only possible if there are multiple precision clock
sources.
6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
■
■
■
■
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50% duty
cycle clocks, system clock resynchronization logic, and deglitch
logic. The outputs from each digital clock tree can be routed into
the digital system interconnect and then brought back into the
clock system as an input, allowing clock chaining of up to 32 bits.
Document Number: 001-66235 Rev. *A
The system clock is used to select and supply the fastest clock
in the system for general system clock requirements and clock
synchronization of the PSoC device.
Bus clock 16-bit divider uses the system clock to generate the
system’s bus clock used for data transfers and the CPU. The
CPU clock is directly derived from the bus clock.
Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, the UDBs and fixed function timer/counter/PWMs can
also generate clocks.
Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as ADCs and mixers.
The analog clock dividers include skew control to ensure that
critical analog events do not occur simultaneously with digital
switching events. This is done to reduce analog system noise.
PRELIMINARY
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
6.2 Power System
The power system consists of separate analog, digital, and I/O
supply pins, labeled V
also includes two internal 1.8 V regulators that provide the digital
(V
The output pins of the regulators (V
pins must have capacitors connected as shown in
The two V
trace as possible, and connected to a 1 µF ±10% X5R capacitor.
The power system also contains a sleep regulator and a
hibernate regulator.
CCD
PSoC
) and analog (V
CCD
®
pins must be shorted together, with as short a
5: CY8C55 Family Datasheet
CCA
DDA
) supplies for the internal core logic.
, V
DDD
, and V
CCD
and V
DDIOX
CCA
, respectively. It
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) and the V
Figure
6-4.
DDIO
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