CY8C5568AXI-060 Cypress Semiconductor Corp, CY8C5568AXI-060 Datasheet - Page 101
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CY8C5568AXI-060
Manufacturer Part Number
CY8C5568AXI-060
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY8C5568AXI-060.pdf
(114 pages)
Specifications of CY8C5568AXI-060
Lead Free Status / Rohs Status
Compliant
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11.8.3 SWD Interface
Table 11-68. SWD Interface AC Specifications
11.8.4 TPIU Interface
Table 11-69. TPIU Interface AC Specifications
Document Number: 001-66235 Rev. *A
f_SWDCK
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max
T_SWDI_hold
T_SWDO_valid SWDCK high to SWDIO output
T_SWDO_hold SWDIO output hold after SWDCK low
Notes
41. Based on device characterization (Not production tested).
42. f_SWDCK must also be no more than 1/3 CPU clock frequency.
43. SWV signal frequency and bit rate are limited by GPIO output frequency, see
Parameter
Parameter
SWDIO input hold after SWDCK high
SWDCLK frequency
SWV bit rate
Description
Description
PRELIMINARY
[41]
[41]
3.3 V ≤ V
2.7 V ≤ V
2.7 V ≤ V
USBIO pins
T = 1/f_SWDCK max
T = 1/f_SWDCK max
T = 1/f_SWDCK max
“GPIO AC Specifications”
DDD
DDD
DDD
Conditions
Conditions
PSoC
≤ 5 V
< 3.3 V
< 3.3 V, SWD over
®
5: CY8C55 Family Datasheet
on page 66.
Min
T/4
T/4
T/4
Min
–
–
–
–
–
Typ
Typ
–
–
–
–
–
–
–
–
Page 101 of 114
5.5
33
12
2T/5
Max
Max
7
[42]
–
–
–
[43]
[42]
[42]
Units
Units
MHz
MHz
MHz
Mbit
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