AGLN125V2-VQG100 Actel, AGLN125V2-VQG100 Datasheet - Page 65

• Manufacturer Part Number: AGLN125V2-VQG100
• Manufacturer: Actel

Figure 2-20 • Output DDR Timing Diagram
Table 2-74 • Output DDR Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
Data_F
Data_R
CLK
CLR
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
Out
DDOMAX
For specific junction temperature and voltage supply levels, refer to
values.
6
Timing Characteristics
t
Commercial-Case Conditions: T
DDROCLR2Q
1
1.5 V DC Core Voltage
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
t
DDROREMCLR
t
DDROREMCLR
7
2
t
t
DDROCLKQ
DDROHD1
7
t
J
DDROSUD2
= 70°C, Worst-Case V
8
A dv a n c e v 0. 3
3
Description
2
t
DDROHD2
8
CC
= 1.425 V
IGLOO nano DC and Switching Characteristics
4
9
3
Table 2-6 on page 2-6
t
DDRORECCLR
9
10
4
5
1.07
0.67
0.67
0.00
0.00
1.38
0.00
0.23
0.19
0.28
Std.
0.31
TBD
for derating
10
Units
MHz
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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