ADRF6602ACPZ-R7 Analog Devices Inc, ADRF6602ACPZ-R7 Datasheet - Page 7

• Manufacturer Part Number: ADRF6602ACPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of ADRF6602ACPZ-R7

• Lead Free Status / Rohs Status: Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4, 7, 11, 15, 20,
21, 23, 24, 25,
28, 30, 31, 35
5
6
8
9
10
12
13
14
16
17, 34
18, 19
Mnemonic
VCC1
DECL3P3
CP
GND
R
REF_IN
MUXOUT
DECL2P5
VCC2
DATA
CLK
LE
PLL_EN
VCC_LO
IFP, IFN
SET
Description
Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.
Decoupling Node for 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground.
Charge Pump Output Pin. Connect to VTUNE through loop filter.
Ground. Connect these pins to a low impedance ground plane.
Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using
Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In
this mode, no external R
can be externally adjusted according to the following equation:
Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz.
Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect
signal. The output is selected by programming the appropriate register.
Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground.
Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.
Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits.
Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the
eight registers. The relevant latch is selected by the three control bits of the 24-bit word.
PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is
automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the
internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be
used to switch modes.
Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled
with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin.
Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes.
=
⎛
⎜
⎜
⎝
217
4 .
DECL3P3
DECL2P5
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A
MUXOUT
×
REF_IN
LOW IMPEDANCE GROUND PLANE.
VCC1
VCC2
R
GND
GND
SET
CP
⎞
⎟
⎟
⎠
10
1
2
3
4
5
6
7
8
9
SET
−
37.8
is required. If Bit DB18 is set to 1, the four nominal charge pump currents (I
Figure 3. Pin Configuration
Rev. C | Page 7 of 32
Ω
PIN 1
INDICATOR
ADRF6602
(Not to Scale)
TOP VIEW
30 GND
29 IP3SET
28 GND
27 VCC_V2I
26 RF
25 GND
24 GND
23 GND
22 VCC_MIX
21 GND
IN
ADRF6602
NOMINAL
)