MAX97001EWP+T Maxim Integrated Products, MAX97001EWP+T Datasheet - Page 22

• Manufacturer Part Number: MAX97001EWP+T
• Description: IC AUDIO SUBSYSTEM 20WLP
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive™r
• Type: Class Dr

Specifications of MAX97001EWP+T

• Output Type: 1-Channel (Mono) with Stereo Headphones
• Max Output Power X Channels @ Load: 920mW x 1 @ 8 Ohm; 37mW x 2 @ 16 Ohm
• Voltage - Supply: 2.7 V ~ 5.5 V
• Features: Depop, Differential Inputs, I²C, Mute, Shutdown, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 20-WLP
• Product: Class-D
• Output Power: 550 mW, 700 mW, 920 mW
• Available Set Gain: 12 dB
• Common Mode Rejection Ratio (min): 32 dB, 55 dB
• Thd Plus Noise: 0.05 %
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Current: 2.7 V
• Maximum Power Dissipation: 1040 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Signal Type: Differential, Single
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential
• Supply Voltage (max): 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX97001EWP+T

Audio Subsystem with Mono Class D Speaker
and Class H Headphone Amplifiers
In addition to the cost and size disadvantages of
the DC-blocking capacitors required by conventional
headphone amplifiers, these capacitors limit the ampli-
fier’s low-frequency response and can distort the audio
signal. Previous attempts at eliminating the output-
coupling capacitors involved biasing the headphone
return (sleeve) to the DC-bias voltage of the headphone
amplifiers. This method raises some issues:
U The sleeve is typically grounded to the chassis. Using
U During an ESD strike, the amplifier’s ESD structures are
U When using the headphone jack as a line out to other
The MAX97001’s dual-mode charge pump generates
both the positive and negative power supply for the
headphone amplifier. To maximize effficiency, both the
charge pump’s switching frequency and output voltage
change based on signal level.
When the input signal level is less than 10% of V
the switching frequency is reduced to a low rate. This
minimizes switching losses in the charge pump. When
the input signal exceeds 10% of V
quency increases to support the load current.
For input signals below 25% of V
generates Q(V
the amplifier’s power stage and thus improves efficiency.
Input signals that exceed 25% of V
pump to output QV
for full output power from the headphone amplifier.
To prevent audible glitches when transitioning from the
Q(V
charge pump transitions very quickly. This quick change
draws significant current from V
transition. The bypass capacitor on V
required current and prevent droop on V
22
the midrail biasing approach, the sleeve must be isolat-
ed from system ground, complicating product design.
the only path to system ground. Thus, the amplifier must
be able to withstand the full energy from an ESD strike.
equipment, the bias voltage on the sleeve may conflict
with the ground potential from other equipment, result-
ing in possible damage to the amplifiers.
DD
/2) output mode to the QV
DD
/2) to minimize the voltage drop across
DD
. The higher output voltage allows
DD
DD
DD
DD
DD
for the duration of the
, the charge pump
, the switching fre-
output mode, the
cause the charge
DD
DD
Charge Pump
supplies the
.
DD
Figure 7. Class H Operation
The charge pump’s dynamic switching mode can be
turned off through the I
can then be forced to output either Q(V
regardless of input signal level.
A Class H amplifier uses a Class AB output stage with
power supplies that are modulated by the output signal.
In the case of the MAX97001, two nominal power-supply
differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V
to -1.8V) are available from the charge pump. Figure 7
shows the operation of the output voltage dependent
power supply.
To minimize power consumption when using the head-
phone amplifier, enable the low-power mode. In this
mode, the headphone mixers and volume control are
bypassed and shutdown.
The MAX97001 uses a slave address of 0x9A or
1001101R/W. The address is defined as the 7 most signifi-
cant bits (MSBs) followed by the read/write bit. Set the read/
write bit to 1 to configure the MAX97001 to read mode. Set
the read/write bit to 0 to configure the MAX97001 to write
mode. The address is the first byte of information sent to
the MAX97001 after the START (S) condition.
V
V
-0.9V
-1.8V
TH_H
TH_L
1.8V
0.9V
HPVDD
HPVSS
2
C interface. The charge pump
I
32ms
32ms
2
C Slave Address
Class H Operation
Low-Power Mode
DD
/2) or QV
OUTPUT
VOLTAGE
DD