ATA5830N-PNQW Atmel, ATA5830N-PNQW Datasheet - Page 22

• Manufacturer Part Number: ATA5830N-PNQW
• Manufacturer: Atmel

Specifications of ATA5830N-PNQW

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.4.1.1
22
Atmel ATA5830/ATA5830N
Architectural Overview
This section discusses the AVR
core is to ensure correct program execution. Therefore it must be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 3-5.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next
instruction is pre-fetched from the program memory. This concept enables instructions to be
executed in every clock cycle. The program memory is In- System Reprogrammable Flash
memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a sin-
gle clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In
a typical ALU operation, two operands are output from the Register File, the operation is exe-
cuted, and the result is stored back in the Register File – in one clock cycle.
Architectural Overview
Control Lines
Instruction
Instruction
Program
Decoder
Memory
Register
Flash
ROM
®
Program
Counter
core architecture in general. The main function of the CPU
Status and
Registers
EEPROM
Data Bus 8-bit
Purpose
General
Control
SRAM
32 x 8
Data
ALU
Management
I/O Module 1
I/O Module n
Watchdog
Interrupt
Timer
Clock
PortN
Unit
Unit
SPI
9208DS–RKE–07/11