LM49370RL/NOPB National Semiconductor, LM49370RL/NOPB Datasheet - Page 4

• Manufacturer Part Number: LM49370RL/NOPB
• Description: IC AUDIO SUBSYSTEM 1.2W 49USMDXT
• Manufacturer: National Semiconductor
• Series: Boomer®, PowerWise®r
• Type: Class Dr

Specifications of LM49370RL/NOPB

• Output Type: 1-Channel (Mono) with Mono and Stereo Headphones
• Max Output Power X Channels @ Load: 1.2W x 1 @ 8 Ohm; 52mW x 2 @ 16 Ohm
• Voltage - Supply: 2.5 V ~ 5.5 V
• Features: 3D, Depop, I²C, I²S, Microphone, Mute, PCM, Shutdown, SPI, Standby, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 49-MicroSMDxt
• Dc: 07+
• For Use With: LM49370RLEVAL - BOARD EVALUATION LM49370RL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM49370RLTR

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1.0 General Description ......................................................................................................................... 1
2.0 Applications .................................................................................................................................... 1
3.0 Key Specifications ........................................................................................................................... 1
4.0 Features ........................................................................................................................................ 1
5.0 LM49370 Overview .......................................................................................................................... 2
6.0 Typical Application ........................................................................................................................... 3
7.0 Connection Diagrams ....................................................................................................................... 5
8.0 Absolute Maximum Ratings .............................................................................................................. 8
9.0 Operating Ratings ........................................................................................................................... 8
10.0 Electrical Characteristics
11.0 System Control ............................................................................................................................ 14
12.0 Status & Control Registers ............................................................................................................ 18
13.0 Typical Performance Characteristics .............................................................................................. 58
14.0 LM49370 Demonstration Board Schematic Diagram ......................................................................... 91
15.0 Demoboard PCB Layout ............................................................................................................... 92
16.0 Revision History .......................................................................................................................... 98
17.0 Physical Dimensions .................................................................................................................... 99
7.1 PIN TYPE DEFINITIONS ................................................................................................................ 7
A_V
Limits apply for 25°C.
11.1 I
11.2 I
11.3 I
11.4 TRANSFERRING DATA ............................................................................................................. 14
11.5 I
12.1 BASIC CONFIGURATION REGISTER ......................................................................................... 19
12.2 CLOCKS CONFIGURATION REGISTER ...................................................................................... 20
12.3 LM49370 CLOCK NETWORK ..................................................................................................... 21
12.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC ................................................................... 22
12.5 PLL M DIVIDER CONFIGURATION REGISTER ............................................................................ 23
12.6 PLL N DIVIDER CONFIGURATION REGISTER ............................................................................ 24
12.7 PLL P DIVIDER CONFIGURATION REGISTER ............................................................................ 25
12.8 PLL N MODULUS CONFIGURATION REGISTER ......................................................................... 26
12.9 FURTHER NOTES ON PLL PROGRAMMING ............................................................................... 27
12.10 ADC_1 CONFIGURATION REGISTER ....................................................................................... 30
12.11 ADC_2 CONFIGURATION REGISTER ....................................................................................... 31
12.12 AGC_1 CONFIGURATION REGISTER ...................................................................................... 32
12.13 AGC_2 CONFIGURATION REGISTER ...................................................................................... 33
12.14 AGC_3 CONFIGURATION REGISTER ...................................................................................... 34
12.15 AGC OVERVIEW ..................................................................................................................... 35
12.16 MIC_1 CONFIGURATION REGISTER ........................................................................................ 36
12.17 MIC_2 CONFIGURATION REGISTER ........................................................................................ 37
12.18 SIDETONE ATTENUATION REGISTER ..................................................................................... 38
12.19 CP_INPUT CONFIGURATION REGISTER ................................................................................. 38
12.20 AUX_LEFT CONFIGURATION REGISTER ................................................................................. 39
12.21 AUX_RIGHT CONFIGURATION REGISTER ............................................................................... 39
12.22 DAC CONFIGURATION REGISTER .......................................................................................... 40
12.23 CP_OUTPUT CONFIGURATION REGISTER .............................................................................. 41
12.24 AUX_OUTPUT CONFIGURATION REGISTER ............................................................................ 41
12.25 LS_OUTPUT CONFIGURATION REGISTER .............................................................................. 41
12.26 HP_OUTPUT CONFIGURATION REGISTER .............................................................................. 42
12.27 EP_OUTPUT CONFIGURATION REGISTER .............................................................................. 42
12.28 DETECT CONFIGURATION REGISTER .................................................................................... 43
12.29 HEADSET DETECT OVERVIEW ............................................................................................... 44
12.30 STATUS REGISTER ................................................................................................................ 47
12.31 3D CONFIGURATION REGISTER ............................................................................................. 48
12.32 I2S PORT MODE CONFIGURATION REGISTER ........................................................................ 49
12.33 I2S PORT CLOCK CONFIGURATION REGISTER ....................................................................... 50
12.34 DIGITAL AUDIO DATA FORMATS ............................................................................................. 51
12.35 PCM PORT MODE CONFIGURATION REGISTER ...................................................................... 52
12.36 PCM PORT CLOCK CONFIGURATION REGISTER ..................................................................... 53
12.37 SRC CONFIGURATION REGISTER .......................................................................................... 54
12.38 GPIO CONFIGURATION REGISTER ......................................................................................... 56
12.39 DAC PATH COMPENSATION FIR CONFIGURATION REGISTERS .............................................. 56
DD
2
2
2
2
= 3.3V, LS_V
C SIGNALS ............................................................................................................................ 14
C DATA VALIDITY .................................................................................................................. 14
C START AND STOP CONDITIONS .......................................................................................... 14
C TIMING PARAMETERS ....................................................................................................... 16
DD
.............................................................................................................................. 8
= 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated.
(Notes 1, 2)
Table of Contents
Unless otherwise stated PLL_V
4
DD
= 3.3V, D_V
DD
= 3.3V, BB_V
DD
= 1.8V,