LM49370RL/NOPB National Semiconductor, LM49370RL/NOPB Datasheet - Page 21
LM49370RL/NOPB
Manufacturer Part Number
LM49370RL/NOPB
Description
IC AUDIO SUBSYSTEM 1.2W 49USMDXT
Manufacturer
National Semiconductor
Series
Boomer®, PowerWise®r
Type
Class Dr
Datasheet
1.LM49370RLNOPB.pdf
(100 pages)
Specifications of LM49370RL/NOPB
Output Type
1-Channel (Mono) with Mono and Stereo Headphones
Max Output Power X Channels @ Load
1.2W x 1 @ 8 Ohm; 52mW x 2 @ 16 Ohm
Voltage - Supply
2.5 V ~ 5.5 V
Features
3D, Depop, I²C, I²S, Microphone, Mute, PCM, Shutdown, SPI, Standby, Volume Control
Mounting Type
Surface Mount
Package / Case
49-MicroSMDxt
Dc
07+
For Use With
LM49370RLEVAL - BOARD EVALUATION LM49370RL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LM49370RLTR
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12.3 LM49370 CLOCK NETWORK
The audio ADC operates at 125*fs ( or 128*fs), so it requires a 1.000 MHz (or 1.024MHz) clock to sample at 8 kHz (at point C as
marked on the following diagram). If the stereo DAC is running at 125*fs (or128*fs), it requires a 12.000MHz (or 12.288MHz) clock
(at point B) for 48 kHz data. It is expected that the PLL is used to drive the audio system operating at 125*fs unless a 12.000 MHz
master clock is supplied or the sample rate is always a multiple of 8 kHz. In this case the PLL can be bypassed to reduce power,
with clock division being performed by the Q and R dividers instead. The PLL can also be bypassed if the system is running at
128*fs and a 12.288MHz master clock is supplied and the sample rate is a multiple of 8kHz. The PLL can also use the I
2
S clock
input as a source. In this case, the audio DAC uses the clock from the output of the PLL and the audio ADC either uses the PLL
output divided by 2*F
/F
or a system clock divided by Q, this allows n*8 kHz recording and 44.1 kHz playback.
S(DAC)
S(ADC)
MCLK must be less than or equal to 30 MHz. I2S_CLK and PCM_CLK should be below 6.144MHz.
When operating at 125*fs, the LM49370 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A. When operating
at 128*fs, the LM49370 is designed to work from a 12.288MHz or 11.2896 MHz clock at point A. This is used to drive the power
management and control logic. Performance may not meet the electrical specifications if the frequency at this point deviates
significantly beyond this range.
20191710
FIGURE 6. LM49370 Clock Network
21
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