ISD5216SY Nuvoton Technology Corporation of America, ISD5216SY Datasheet - Page 49

• Manufacturer Part Number: ISD5216SY
• Description: IC VOICE REC/PLAY 8-16MIN 28SOIC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISL5216r

Specifications of ISD5216SY

• Interface: I²C
• Filter Pass Band: 1.8 ~ 3.7kHz
• Duration: 8 ~ 16 Min
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Memo Record mode sets the chip up to record from the local microphone into the chip’s Multilevel
Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down
since they are not active in this mode. The path to be used is microphone input to AGC amplifier, then
through to the INPUT SOURCE MUX, to the SUM1 SUMMING amplifier. From there, the path goes
through the FILTER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the
MULTILEVEL STORAGE ARRAY. In this example, we will select the 5.3 kHz sample rate. The rest of
the chip may be powered down.
1. Power up the AGC amplifier - Bit AGPD controls the power up state of the AGC amplifier. This is
2. Select the AGC amplifier through the INPUT SOURCE MUX —Bit INS0 controls the state of the
3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier— Bits S1M0 and S1M1
4. Select the SUM1 SUMMING amplifier path through the FILTER MUX— Bit FLS0 controls the
5. Deselect the signal compression- Bit AMT0 controls the signal compression. This is bit D7 of
6. Power up the LOW PASS FILTER— Bit FLPD controls the power up state of the LOW PASS
7. Select the 5.3 kHz sample rate —Bits FLD0 and FLD1 select the Low Pass filter setting and
8. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier – BITS S2M0 and
9. Power up the Internal Oscillator— Bit OSPD controls the power up state of the Internal
To set up the chip for Memo Record, the configuration registers are set up as follows:
CFG0=0000 0100 0000 0001 (hex 0401).
CFG1=0000 0001 0100 1000 (hex 0148).
CFG2=0000 0000 0000 0011 (hex 0003).
bit D0 of CFG1 and must be set to ZERO to power up this stage.
INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the AGC am-
plifier.
control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8, respectively, of
CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the INPUT
SOURCE MUX (only) path.
state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1
SUMMING amplifier path.
CFG0 and it must be set to ZERO.
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE.
S2M1 control the state of the SUM2 SUMMING amplifier.
respectively, of CFG1, set D5 to ZERO and D6 to ONE to select the LOW PASS FILTER (only)
path.
Oscillator. This is bit D8 of CFG0 and it must be set to ZERO to power up the Internal Oscillator.
7.10.11. Memo Record
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Publication Release Date: July 17, 2007
These are bits D5 and D6,
ISD5216
Revision B.5