SC16C550IA44,529 NXP Semiconductors, SC16C550IA44,529 Datasheet - Page 29

• Manufacturer Part Number: SC16C550IA44,529
• Description: IC UART SINGLE W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C550IA44,529

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3264-5; 935270058529; SC16C550IA44-S

Philips Semiconductors
9397 750 11619
Product data
7.8 Modem Status Register (MSR)
Table 19:
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C550 is connected. Four bits of
this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
Table 20:
Bit
0
Bit
7
6
5
4
3
2
Symbol
LSR[0]
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
Line Status Register bits description
Modem Status Register bits description
Description
Receive data ready.
Rev. 05 — 19 June 2003
Description
Data Carrier Detect. DCD (Active-HIGH, logical 1). Normally this bit is
the complement of the DCD input. In the loop-back mode this bit is
equivalent to the OUT2 bit in the MCR register.
Ring Indicator. RI (Active-HIGH, logical 1). Normally this bit is the
complement of the RI input. In the loop-back mode this bit is equivalent
to the OUT1 bit in the MCR register.
Data Set Ready. DSR (Active-HIGH, logical 1). Normally this bit is the
complement of the DSR input. In loop-back mode this bit is equivalent to
the DTR bit in the MCR register.
Clear To Send. CTS. CTS functions as hardware flow control signal
input if it is enabled via EFR[7]. The transmit holding register flow control
is enabled/disabled by MSR[4]. Flow control (when enabled) allows
starting and stopping the transmissions based on the external modem
CTS signal. A logic 1 at the CTS pin will stop SC16C550 transmissions
as soon as current character has finished transmission. Normally
MSR[4] is the complement of the CTS input. However, in the loop-back
mode, this bit is equivalent to the RTS bit in the MCR register.
DCD
RI
Logic 0 = No data in receive holding register or FIFO (normal default
condition).
Logic 1 = Data has been received and is saved in the receive holding
register or FIFO.
Logic 0 = No DCD change (normal default condition).
Logic 1 = The DCD input to the SC16C550 has changed state since
the last time it was read. A modem Status Interrupt will be generated.
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C550 has changed from a logic 0 to
a logic 1. A modem Status Interrupt will be generated.
[1]
[1]
UART with 16-byte FIFO and IrDA encoder/decoder
…continued
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C550
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