SC16C2550IA44,529 NXP Semiconductors, SC16C2550IA44,529 Datasheet - Page 22

• Manufacturer Part Number: SC16C2550IA44,529
• Description: IC UART DUAL W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C2550IA44,529

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 3.5 V ~ 4.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3260-5; 935270019529; SC16C2550IA44-S

Philips Semiconductors
9397 750 11621
Product data
7.5 Line Control Register (LCR)
Table 12:
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 13:
Bit
7-6
5-4
3-1
0
Bit
7
6
5-3
2
1-0
Interrupt Status Register bits description
Line Control Register bits description
Symbol
ISR[7-6]
ISR[5-4]
ISR[3-1]
ISR[0]
Symbol
LCR[7]
LCR[6]
LCR[5-3]
LCR[2]
LCR[1-0]
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
Rev. 03 — 19 June 2003
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are
not being used in the 16C450 mode. They are set to a logic 1
when the FIFOs are enabled in the SC16C2550 mode.
INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status.
Description
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Programs the parity conditions (see
Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Table
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
16).
Table
SC16C2550
14).
encoder/decoder
Table
Table
11).
15).
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