A54SX32-2BG329IX3 MICROSEMI, A54SX32-2BG329IX3 Datasheet - Page 7
A54SX32-2BG329IX3
Manufacturer Part Number
A54SX32-2BG329IX3
Description
Manufacturer
MICROSEMI
Datasheet
1.A54SX32-2BG329IX3.pdf
(64 pages)
Specifications of A54SX32-2BG329IX3
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Chip Architecture
The SX family chip architecture provides a unique
approach to module organization and chip routing that
delivers the best register/logic mix for a wide variety of
new and emerging applications.
Module Organization
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called clusters. There are two types of
clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
Figure 1-3 •
Figure 1-4 •
Internal Logic
CLKA, CLKB,
Connect
C-Cell
Cluster Organization
Direct
HCLK
Input
Cluster 1
CKS
S0
Routed Data Input
Type 1 SuperCluster
D0
D1
D2
D3
DB
R-Cell
CKP
S1
D
Cluster 2
PSETB
CLRB
Q
Y
A0
v3.2
B0
Sa
To increase design efficiency and device performance,
Actel has further organized these modules into
SuperClusters
grouping of Type 1 clusters. SuperCluster 2 is a two-wide
group containing one Type 1 cluster and one Type 2
cluster. SX devices feature more SuperCluster 1 modules
than SuperCluster 2 modules because designers typically
require significantly more combinatorial logic than flip-
flops.
D0
D1
D2
D3
DB
Cluster 2
A1
Type 2 SuperCluster
(Figure
Sb
B1
A0
C-Cell
1-4). SuperCluster 1 is a two-wide
B0
Sa
Y
Cluster 1
A1
B1
Sb
SX Family FPGAs
Y
1-3
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