A54SX32A-TQG100 Actel, A54SX32A-TQG100 Datasheet
A54SX32A-TQG100
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A54SX32A-TQG100 Summary of contents
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... Std, –1, –2 –F, Std, –1, –2, – 208 208 100, 144 100, 144 – – 144 144, 256 – – Programming Technology A54SX32A A54SX72A 32,000 72,000 48,000 108,000 2,880 6,036 1,800 4,024 1,080 2,012 1,980 4,024 249 360 3 3 ...
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... Ordering Information A54SX16A 2 Part Number A54SX08A = 12,000 System Gates A54SX16A = 24,000 System Gates A54SX32A = 48,000 System Gates A54SX72A = 108,000 System Gates Notes: 1. For more information about the CQFP package options, refer to the 2. All –3 speed grades have been discontinued. Device Resources ...
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... Automotive Military MIL-STD-883B Notes: 1. For more information regarding automotive products, refer to the 2. For more information regarding Mil-Temp and ceramic packages, refer to the Contact your Actel Sales representative for more information on availability. A54SX16A A54SX32A C,I,A,M C,I,A,M C,I,A,M C,I,A,M C,I,A,M C,I,A,M C,I,M C,I,M ...
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SX-A Family FPGAs Table of Contents General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Tungsten Plug Contact Note: The A54SX72A device has four layers of metal with the antifuse between Metal 3 and Metal 4. The A54SX08A, A54SX16A, and A54SX32A devices have three layers of metal with the antifuse between Metal 2 and Metal 3. Figure 1-1 • SX-A Family Interconnect Elements SX-A Family Architecture The SX-A family’ ...
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... The Actel SX-A family provides two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring asynchronous clear, ...
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... In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. The Actel segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the ...
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SX-A Family FPGAs Figure 1-5 • DirectConnect and FastConnect for Type 1 SuperClusters Figure 1-6 • DirectConnect and FastConnect for Type 2 SuperClusters 1 -4 DirectConnect • No Antifuses • 0.1 ns Maximum Routing Delay FastConnect • One Antifuse • ...
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... Constant Load Clock Network HCLKBUF From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI v5.3 SX-A Family FPGAs (Figure 1-9 on page 1-6). QCLK pins can Global Clock Networks and Using A54SX72A and application notes. Figure 1-10 on 1-15. A54SX32A A54SX72A Clock Network 1-5 ...
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SX-A Family FPGAs Quadrant 2 QCLKINT (to array) Quadrant 0 QCLKINT (to array) Figure 1-9 • SX-A QCLK Architecture Figure 1-10 • A54SX72A Routed Clock and QCLK Buffer QCLKBUFS 4 Quadrant 3 5:1 5:1 QCLKINT (to array) ...
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... Other Architectural Features Technology The Actel SX-A family is implemented on a high-voltage, twin-well CMOS process using 0.22 μ / 0.25 μ design rules. The metal-to-metal antifuse is comprised of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed ('on' state) resistance of 25 Ω with capacitance of 1.0 fF for low signal impedance ...
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... Table 1-4 • Power-Up Time at which I/Os Become Active Supply Ramp Rate 0.25 V/μs 0.025 V/μs μs Units A54SX08A 10 A54SX16A 10 A54SX32A 10 A54SX72A are reached. which the I/Os behave according to the user’s design for and V do not an SX-A device at room temperature for various ramp-up ...
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... TMS and TDI pins are not present in flexible JTAG mode. To select the Flexible mode, uncheck the Reserve JTAG box in the Device Selection Wizard dialog in the Actel Designer software. In Flexible mode, TDI, TCK, and TDO pins may function as user I/Os or BST pins. The functionality is controlled by the BST Test Access Port (TAP) controller ...
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... IDCODE HighZ CLAMP Diagnostic BYPASS Reserved Table 1-8 • JTAG Instruction Code Device Process A54SX08A 0.22 µ A54SX16A 0.22 µ 0.25 µ A54SX32A 0.2 2µ 0.25 µ A54SX72A 0.22 µ 0.25 µ Binary Code 00000 00001 00010 00011 00100 01110 01111 ...
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... JTAG pins. The Silicon Explorer II diagnostic hardware is used to control the TDI, TCK, TMS, and TDO pins to select the desired nets for debugging. The user assigns the selected internal nets in Actel Silicon Explorer II software to the PRA/PRB output pins for observation. Silicon Explorer II automatically places the device into JTAG mode ...
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... Since these pins are active during probing, critical input signals through these pins are not available. In addition, the security fuse must not be programmed to preserve probing capabilities. Actel recommends that you use a 70 Ω series termination resistor on every probe connector (TDI, TCK, TMS, TDO, PRA, PRB). The 70 Ω ...
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... Design Environment The SX-A family of FPGAs is fully supported by both Actel ® Libero Integrated Design Environment (IDE) and Designer FPGA development software. Actel Libero IDE is a design management environment, integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools ...
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... Using A54SX72A and RT54SX72S Quadrant Clocks http://www.actel.com/documents/QCLK_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/Antifuse_Security_AN.pdf Actel eX, SX-A, and RTSX-S I/Os http://www.actel.com/documents/AntifuseIO_AN.pdf Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications http://www.actel.com/documents/HotSwapColdSparing_AN.pdf Programming Antifuse Devices http://www.actel.com/documents/AntifuseProgram_AN.pdf Datasheets HiRel SX-A Family FPGAs http://www ...
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Pin Description CLKA/B, I/O Clock A and B These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL, LVTTL, LVCMOS2, 3.3 V PCI PCI specifications. The clock input is buffered prior ...
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... V Power Supply Range (V ) CCI Typical SX-A Standby Current Table 2-3 • Typical Standby Current for SX-A at 25°C with V Product A54SX08A A54SX16A A54SX32A A54SX72A Table 2-4 • Supply Voltages V CCA 2.5 V 2.5 V Note: *3.3 V PCI is not 5 V tolerant due to the clamp diode, but instead is 3.3 V tolerant. ...
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... Input Leakage Current Tristate Output Leakage Current Input Transition Time I/O Capacitance IO I Standby Current CC IV Curve* Can be derived from the IBIS model on the web. Note: *The IBIS model can be found at http://www.actel.com/download/ibis/default.aspx –1 mA – GND CCI Parameter = –100 μ –1 mA =– ...
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PCI Compliance for the SX-A Family The SX-A family supports 3.3 V and 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 2-7 • DC Specifications (5 V PCI Operation) Symbol Parameter V Supply ...
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SX-A Family FPGAs Table 2-8 • AC Specifications (5 V PCI Operation) Symbol Parameter I Switching Current High OH(AC) (Test Point) I Switching Current Low OL(AC) (Test Point) I Low Clamp Current CL slew Output Rise Slew Rate R slew ...
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Figure 2-1 shows the 5 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family. 200 MAX Spec 150.0 100.0 50.0 0.0 0 0.5 –50 MIN Spec –100.0 –150.0 –200.0 ...
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SX-A Family FPGAs Table 2-10 • AC Specifications (3.3 V PCI Operation) Symbol Parameter I Switching Current High OH(AC) (Test Point) I Switching Current Low OL(AC) (Test Point) I Low Clamp Current CL I High Clamp Current CH slew Output ...
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Figure 2-2 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family. 150 MAX Spec 100.0 50.0 0.0 0 0.5 –50 MIN Spec –100.0 –150.0 Figure 2-2 ...
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SX-A Family FPGAs Power Dissipation A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package used, the operating ...
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... A54SX08A A54SX16A 1.70 pF 2.00 pF 1.50 pF 1.50 pF 1.30 pF 1.30 pF 7.40 pF 7.40 pF 1.05 pF 1.05 pF 0.85 pF 0.85 pF 30.00 pF 55.00 pF 35.00 pF 50.00 pF v5.3 SX-A Family FPGAs A54SX32A A54SX72A 2.00 pF 1.80 pF 1.30 pF 1.50 pF 1.30 pF 1.30 pF 7.40 pF 7.40 pF 1.05 pF 1.05 pF 0.85 pF 0.85 pF 110.00 pF 240.00 pF 90.00 pF 310.00 pF 2-9 ...
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... Average Output Switching Rate (fp) = f/10 Average CLKA Rate (fq1) = f/2 Average CLKB Rate (fq2) = f/2 Average HCLK Rate (fs1 HCLK loads (s1) = 20% of R-cells To assist customers in estimating the power dissipations of their designs, Actel has published the Power Calculator worksheet v5.3 eX, SX-A and RT54SX-S ...
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... Plastic Ball Grid Array (PBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Notes: 1. The A54SX08A PQ208 has no heat spreader. 2. The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A – θ ...
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... The device's power consumption must be lower than the calculated maximum power dissipation by the package. The power consumption of a device can be calculated using the Actel power calculator. If the power consumption is higher than the device's maximum allowable power dissipation, then a heat sink can be attached on top of the case or the airflow inside the system must be increased ...
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... The heat sink performance can be significantly improved with the presence of airflow. Carefully estimating thermal resistance is important in the long-term reliability of an Actel FPGA. Design engineers should always correlate the power consumption of the device with the maximum allowable power dissipation of the package selected for that device, using the provided thermal resistance data ...
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SX-A Family FPGAs SX-A Timing Model Input Delays I/O Module t = 0.6 ns INYH Routed t = 3.0 ns RCKH Clock (100% Load) I/O Module t = 0.6 ns INYH Hardwired Clock t = 1.8 ns HCKH Note: *Values ...
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Output Buffer Delays 50% 50% GND V OH 1.5 V Out 1 DLH Figure 2-4 • Output Buffer Delays AC Test Loads Load 1 (Used to measure propagation delay) To the Output Under ...
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SX-A Family FPGAs Input Buffer Delays PAD INBUF 1 Out 50% GND t t INY INY Figure 2-6 • Input Buffer Delays Cell Timing Characteristics D t SUD CLK Q CLR PRESET ...
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Timing Characteristics Timing characteristics for SX-A devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input characteristics are common to all SX-A family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after ...
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SX-A Family FPGAs Timing Characteristics Table 2-14 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC t ...
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Table 2-14 • A54SX08A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description t Input Data Pad to Y High 5 V PCI INYH t Input Data Pad to Y Low 5 V PCI INYL t Input Data Pad to ...
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SX-A Family FPGAs Table 2-15 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...
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Table 2-16 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse ...
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SX-A Family FPGAs Table 2-17 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...
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Table 2-18 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2.5 V LVCMOS Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Data-to-Pad High to Low—low slew DHLS t Enable-to-Pad, Z ...
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SX-A Family FPGAs Table 2-19 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 1 3.3 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL ...
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Table 2-20 • A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad, Z ...
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SX-A Family FPGAs Table 2-21 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 2 C-Cell Propagation Delays t Internal Array Module PD 3 Predicted Routing Delays Routing Delay, Direct DC Connect ...
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Table 2-21 • A54SX16A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description t Input Data Pad to Y High 5 V PCI INYH t Input Data Pad to Y Low 5 V PCI INYL t Input Data Pad to ...
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SX-A Family FPGAs Table 2-22 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...
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Table 2-23 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse ...
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SX-A Family FPGAs Table 2-24 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...
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Table 2-25 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2.5 V LVCMOS Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Data-to-Pad High to Low—low slew DHLS t Enable-to-Pad, Z ...
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SX-A Family FPGAs Table 2-26 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2 3.3 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL ...
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Table 2-27 • A54SX16A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad, Z ...
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... SX-A Family FPGAs Table 2-28 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 2 C-Cell Propagation Delays t Internal Array Module PD 3 Predicted Routing Delays Routing Delay, Direct DC Connect Routing Delay, Fast Connect Routing Delay RD1 Routing Delay RD2 Routing Delay RD3 ...
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... Table 2-28 • A54SX32A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description t Input Data Pad to Y High 5 V PCI INYH t Input Data Pad to Y Low 5 V PCI INYL t Input Data Pad to Y High 5 V TTL INYH t Input Data Pad to Y Low 5 V TTL ...
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... SX-A Family FPGAs Table 2-29 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse Width High HPWH t Minimum Pulse Width Low ...
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... Table 2-30 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse Width High HPWH t Minimum Pulse Width Low HPWL t Maximum Skew ...
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... SX-A Family FPGAs Table 2-31 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) t Minimum Pulse Width High HPWH t Minimum Pulse Width Low ...
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... Table 2-32 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2.5 V LVCMOS Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Data-to-Pad High to Low—low slew DHLS t Enable-to-Pad ENZL t Data-to-Pad L—low slew ENZLS t Enable-to-Pad ENZH t Enable-to-Pad ENLZ t Enable-to-Pad ...
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... SX-A Family FPGAs Table 2-33 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2 3.3 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad ENZH t Enable-to-Pad ENLZ t Enable-to-Pad ENHZ 3 d Delta Low to High TLH 3 d Delta High to Low THL 3 ...
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... Table 2-34 • A54SX32A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad ENZH t Enable-to-Pad ENLZ t Enable-to-Pad ENHZ 3 d Delta Low to High TLH 3 d Delta High to Low THL ...
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SX-A Family FPGAs Table 2-35 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 2 C-Cell Propagation Delays t Internal Array Module PD 3 Predicted Routing Delays Routing Delay, Direct DC Connect ...
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Table 2-35 • A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description t Input Data Pad to Y High 5 V PCI INYH t Input Data Pad to Y Low 5 V PCI INYL t Input Data Pad to ...
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SX-A Family FPGAs Table 2-36 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...
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Table 2-36 • A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions V Parameter Description t Input Low to High (100% Load) QCKH (Pad to R-cell Input) t Input High to Low (100% Load) QCHKL (Pad to R-cell Input) t Minimum Pulse ...
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SX-A Family FPGAs Table 2-37 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...
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Table 2-37 • A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions V Parameter Description t Input Low to High (100% Load) QCKH (Pad to R-cell Input) t Input High to Low (100% Load) QCHKL (Pad to R-cell Input) t Minimum Pulse ...
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SX-A Family FPGAs Table 2-38 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description Dedicated (Hardwired) Array Clock Networks t Input Low to High HCKH (Pad to R-cell Input) t Input High to Low HCKL (Pad to R-cell Input) ...
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Table 2-38 • A54SX72A Timing Characteristics (Continued) (Worst-Case Commercial Conditions V Parameter Description t Input Low to High (100% Load) QCKH (Pad to R-cell Input) t Input High to Low (100% Load) QCHKL (Pad to R-cell Input) t Minimum Pulse ...
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SX-A Family FPGAs Table 2-39 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2.5 V LVCMOS Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Data-to-Pad High to Low—low slew DHLS ...
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Table 2-40 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description 2 3.3 V PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL t Enable-to-Pad, Z ...
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SX-A Family FPGAs Table 2-41 • A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V Parameter Description PCI Output Module Timing t Data-to-Pad Low to High DLH t Data-to-Pad High to Low DHL t Enable-to-Pad ENZL ...
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... Package Pin Assignments 208-Pin PQFP 208 1 Figure 3-1 • 208-Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 208-Pin PQFP v5.3 SX-A Family FPGAs 3-1 ...
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... GND 63 I/O I/O 64 TRST, I/O TRST, I/O 65 I/O I/O 66 I/O I/O 67 I/O I/O 68 I/O I/O 69 I/O I/O 70 v5.3 208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I CCI CCI CCI CCA ...
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... I/O I/O 136 I/O I/O 137 TDO, I/O 138 I/O I/O 139 GND GND 140 v5.3 SX-A Family FPGAs 208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function NC I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O I/O 205 I/O I/O 206 I/O I/O 207 I/O I/O 208 I/O I/O I/O I/O v5.3 208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKA CLKA CLKB ...
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... TQFP 100 1 Figure 3-2 • 100-Pin TQFP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 100-Pin TQFP v5.3 SX-A Family FPGAs 3-5 ...
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... I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 PRB, I CCA v5.3 100-TQFP A54SX08A A54SX16A A54SX32A Function Function Function GND GND GND I/O I/O I/O HCLK HCLK HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O V ...
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... I/O I/O 94 I/O I/O 95 I/O I/O 96 I/O I/O 97 I/O I/O 98 I/O I/O 99 I/O I/O 100 TCK, I/O TCK, I/O A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O V CCI I/O I/O I/O I/O CLKA CLKB NC V CCA ...
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... SX-A Family FPGAs 144-Pin TQFP 144 1 Figure 3-3 • 144-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html 144-Pin TQFP v5.3 ...
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... V 66 CCI V 67 CCA I/O 68 I/O 69 I/O 70 I/O 71 TDO, I/O I/O 72 GND 73 I/O 74 v5.3 SX-A Family FPGAs 144-Pin TQFP A54SX16A A54SX32A Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCI ...
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... V 138 CCI CCI I/O 139 I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 GND I/O v5.3 144-Pin TQFP A54SX08A A54SX16A A54SX32A Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O ...
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... TQFP 176 1 Figure 3-4 • 176-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html. 176-Pin TQFP v5.3 SX-A Family FPGAs 3-11 ...
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... CCA 67 NC 103 68 I/O 104 69 HCLK 105 70 I/O 106 71 I/O 107 72 I/O 108 v5.3 176-Pin TQFP A54SX32A Pin A54SX32A Function Number Function I/O 109 V CCA I/O 110 GND I/O 111 I/O I/O 112 I/O I/O 113 I/O I/O 114 I/O I/O ...
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... TQFP Pin A54SX32A Number Function 145 I/O 146 I/O 147 I/O 148 I/O 149 I/O 150 I/O 151 I/O 152 CLKA 153 CLKB 154 NC 155 GND 156 V CCA 157 PRA, I/O 158 I/O 159 I/O 160 I/O 161 I/O 162 ...
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... SX-A Family FPGAs 329-Pin PBGA Figure 3-5 • 329-Pin PBGA (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html v5 ...
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... I/O B12 GND B13 I/O B14 GND B15 V B16 CCI NC B17 I/O B18 I/O B19 v5.3 SX-A Family FPGAs 329-Pin PBGA A54SX32A Pin A54SX32A Function Number Function I/O B20 I/O I/O B21 I/O I/O B22 GND V B23 V CCI I I/O C2 TDI, I/O ...
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... I/O N23 L3 I L10 GND P3 L11 GND P4 L12 GND P10 L13 GND P11 v5.3 329-Pin PBGA A54SX32A Pin A54SX32A Function Number Function GND P12 GND NC P13 GND I/O P14 GND I/O P20 I/O NC P21 I/O I/O P22 I/O I/O P23 I/O ...
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... PBGA Pin A54SX32A Number Function V22 I/O V23 I/O W1 I/O W2 I/O W3 I/O W4 I/O W20 I/O W21 I/O W22 I/O W23 I/O Y3 I/O Y4 GND Y5 I/O Y6 I/O Y7 I/O Y8 I/O Y9 I/O Y10 I/O Y11 I/O Y12 V CCA Y13 NC Y14 I/O Y15 I/O Y16 ...
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... SX-A Family FPGAs 144-Pin FBGA Figure 3-6 • 144-Pin FBGA (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html v5 ...
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... I/O F4 I/O F5 PRA, I/O F6 I/O F7 I/O F8 I/O F9 I/O F10 I/O F11 I/O F12 v5.3 SX-A Family FPGAs 144-Pin FBGA A54SX16A A54SX32A Function Function I/O I/O I CCI CCI CCI TDI, I/O TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...
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... I/O M4 I/O M5 PRB, I/O M6 I/O M7 I/O M8 I/O M9 I/O M10 I/O M11 V M12 CCA v5.3 144-Pin FBGA A54SX08A A54SX16A A54SX32A Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND ...
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... FBGA Figure 3-7 • 256-Pin FBGA (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html v5.3 SX-A Family FPGAs 3-21 ...
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... I/O D16 I/O E1 I/O E2 I/O E3 GND E4 I/O E5 I/O E6 TDI, I/O E7 GND E8 I/O E9 I/O E10 v5.3 256-Pin FBGA A54SX32A A54SX72A Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKA CLKA I/O I/O I/O I/O I/O I/O I/O I/O ...
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... GND J12 GND J13 GND J14 GND J15 V J16 CCI I/O K1 GND K2 I CCA v5.3 SX-A Family FPGAs 256-Pin FBGA A54SX32A A54SX72A Function Function I/O I/O I/O I/O I/O I/O I/O I/O I CCA CCA CCA TRST, I/O TRST, I/O I/O I/O ...
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... I/O P5 I/O P6 I/O P7 I/O P8 I/O P9 I/O P10 I/O P11 QCLKA P12 PRB, I/O P13 I/O P14 v5.3 256-Pin FBGA A54SX16A A54SX32A A54SX72A Function Function Function I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O ...
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... FBGA A54SX16A A54SX32A Pin Number Function Function P15 I/O I/O P16 I/O I/O R1 I/O I/O R2 GND GND R3 I/O I I/O R5 I/O I/O R6 I/O I/O R7 I/O I/O R8 I/O I/O R9 HCLK HCLK R10 I/O I/O R11 I/O I/O R12 I/O I/O R13 I/O ...
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... SX-A Family FPGAs 484-Pin FBGA 11121314 15161718 19 20212223 242526 Figure 3-8 • 484-Pin FBGA (Top View) Note For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html v5.3 ...
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... AA4 I/O I/O AA5 I/O I/O AA22 I/O I/O AA23 I/O I/O AA24 I/O I/O AA25 NC* I/O Note: *These pins must be left floating on the A54SX32A device. 484-Pin FBGA Pin A54SX32A A54SX72A Number Function Function AA26 NC* I/O AB1 NC* NC AB2 V V CCI ...
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... AE20 I/O I/O AE21 NC* I/O AE22 NC* I/O AE23 NC* I/O AE24 NC* I/O AE25 NC* NC AE26 NC* NC Note: *These pins must be left floating on the A54SX32A device 484-Pin FBGA Pin A54SX32A A54SX72A Number Function Function AF1 NC* NC AF2 NC* NC AF3 NC I/O AF4 NC* I/O AF5 ...
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... CCI D22 GND GND D23 I/O I/O D24 I/O I/O D25 NC* I/O D26 NC* I/O E1 NC* I/O Note: *These pins must be left floating on the A54SX32A device. 484-Pin FBGA Pin A54SX32A A54SX72A Number Function Function E2 NC* I/O E3 I/O I/O E4 I/O I/O E5 GND GND ...
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... I/O L25 I/O I/O L26 I/O I I/O I/O M3 I/O I/O M4 I/O I/O Note: *These pins must be left floating on the A54SX32A device 484-Pin FBGA Pin A54SX32A A54SX72A Number Function Function M5 I/O I/O M10 GND GND M11 GND GND M12 GND ...
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... I/O I/O U23 I/O I/O U24 I/O I/O U25 V V CCI CCI U26 I/O I/O V1 NC* I/O Note: *These pins must be left floating on the A54SX32A device. 484-Pin FBGA Pin A54SX32A A54SX72A Number Function Function V2 NC* I/O V3 I/O I/O V4 I/O I/O V5 I/O ...
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Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version ( v5.2 –3 speed grades have been discontinued. (June 2006) The ...
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... Table 2-13 was updated. Table 2-13 was updated. All timing tables were updated. v3.0 The "Actel Secure Programming Technology with FuseLock™ Prevents Reverse Engineering and Design Theft" section The "Ordering Information" section The "Temperature Grade Offering" section The Figure 1-1 • SX-A Family Interconnect Elements The “ ...
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Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: ...
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... Actel and the Actel logo are registered trademarks of Actel Corporation. Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. ...