IS82C52 Intersil, IS82C52 Datasheet - Page 18

• Manufacturer Part Number: IS82C52
• Description: IC PERIPH UART/BRG 16MHZ 28-PLCC
• Manufacturer: Intersil

Specifications of IS82C52

• Features: Single Chip UART/BRG
• Number Of Channels: 1, UART
• Protocol: RS232C
• Voltage - Supply: 4.5 V ~ 5.5 V
• With Parallel Port: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 28-LCC (J-Lead)
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Function: UART/BRG
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UART Timing Characterization
NOTES:
1. DR bit D7 in USR is updated each time DR changes state. TDRH always from trailing edge of 11th CO(BRG) in last Stop bit.
2. INTR on receive flags OE, FE, PE, and RBRK: INTEN enabled; Respective USR bits updated at this time regardless of interrupt configuration.
3. INTR on MS: INTEN and MIEN enabled; USR bit D4(MS) is updated at this time regardless of INTEN/MIEN.
- INT on OE, FE, PE, RBRK occurs from the trailing edge of the 11th CO(BRG) in the last Stop bit. To avoid OE, RD(RBR) must go low by the
- INTR on MS occurs whenever CTS or DSR input changes state.
trailing edge of the 8th CO(BRG) in the last Stop bit.
DSR/CTS
RTS/DTR
INTR
WR
RD
NOTE 3
18
MCR
(Continued)
TIHM
(22)
FIGURE 20. OTHER TIMING
TWHO
(27)
82C52
82C52
MSR
TRLIL
(23)
April 26, 2006
FN2950.3