SCC2698BC1A84,518 NXP Semiconductors, SCC2698BC1A84,518 Datasheet - Page 13

• Manufacturer Part Number: SCC2698BC1A84,518
• Description: IC UART OCTAL ENHANCED SOT189
• Manufacturer: NXP Semiconductors
• Type: Enhanced octal universal asynchronous receiver/transmitter (Octal UART)r

Specifications of SCC2698BC1A84,518

• Number Of Channels: 8
• Package / Case: 84-LCC (J-Lead)
• Features: False-start Bit Detection
• Fifo's: 3Bit
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 0.1152 MBd
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 30 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 933976250518; SCC2698BC1A84-T; SCC2698BC1A84-T

Philips Semiconductors
Table 2. Register Bit Formats
MR1 (Mode Register 1)
NOTE: *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR2 (Mode Register 2)
CR (Command Register)
SR (Status Register)
2006 Aug 07
NOTE: *Add 0.5 to values shown above for 0–7, if channel is programmed for 5 bits/char.
NOTE: Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter
cannot be loaded
NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status register provides these
bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a reset error status command. In character mode, they
must be reset when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by
using the error reset command (command 4x) or a receiver reset.
Rec’d Break*
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Control
1 = Yes
1 = Yes
RxRTS
0 = No
0 = No
Bit 7
11 = Remote loop
Channel Mode
01 = Auto-echo
10 = Local loop
00 = Normal
RxINT Select
0 = RxRDY
1 = FFULL
Miscellaneous Commands
Framing
1 = Yes
0 = No
Error*
Bit 6
See text
See text
Parity Error*
Error Mode*
1 = Block
0 = Char
Control
TxRTS
1 = Yes
1 = Yes
0 = No
0 = No
Bit 5
Overrun Error
CTS Enable
1 = Yes
1 = Yes
0 = No
0 = No
Bit 4
Tx
11 = Special mode
01 = Force parity
00 = With parity
10 = No parity
Parity Mode
13
Disable Tx
1 = Yes
TxEMT
1 = Yes
0 = No
0 = No
Bit 3
0 = 0.563
1 = 0.625
2 = 0.688
3 = 0.750
Parity Type
Enable Tx
0 = Even
1 = Odd
1 = Yes
TxRDY
1 = Yes
0 = No
0 = No
Bit 2
4 = 0.813
5 = 0.875
6 = 0.938
7 = 1.000
Stop Bit Length*
A = 1.688
8 = 1.563
9 = 1.625
B = 1.750
Disable Rx
1 = Yes
1 = Yes
FFULL
0 = No
0 = No
Bit 1
Bits per Character
SCC2698B
C = 1.813
C = 1.875
E = 1.938
F = 2.000
00 = 5
01 = 6
10 = 7
11 = 8
Product data sheet
Enable Rx
1 = Yes
RxRDY
1 = Yes
0 = No
0 = No
Bit 0