SC16C554DBIA68,512 NXP Semiconductors, SC16C554DBIA68,512 Datasheet - Page 36
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SC16C554DBIA68,512
Manufacturer Part Number
SC16C554DBIA68,512
Description
IC UART QUAD SOT188-2
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C554BIB80528.pdf
(58 pages)
Specifications of SC16C554DBIA68,512
Features
Modem Control Function
Number Of Channels
4, QUART
Fifo's
16 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935276668512
SC16C554DBIA68
SC16C554DBIA68
SC16C554DBIA68
SC16C554DBIA68
NXP Semiconductors
SC16C554B_554DB
Product data sheet
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem, or
other peripheral device to which the SC16C554B/554DB is connected. Four bits of this
register are used to indicate the changed information. These bits are set to a logic 1
whenever a control input from the modem changes state. These bits are set to a logic 0
whenever the CPU reads this register.
Table 21.
[1]
Bit
7
6
5
4
3
2
1
0
Whenever any MSR[3:0] is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Modem Status Register bits description
All information provided in this document is subject to legal disclaimers.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Description
CD (active HIGH, logic 1). Normally this bit is the complement of the CD
input. In the Loopback mode this bit is equivalent to the OP2 bit in the MCR
register.
RI (active HIGH, logic 1). Normally this bit is the complement of the RI input.
In the Loopback mode this bit is equivalent to the OP1 bit in the MCR
register.
DSR (active HIGH, logic 1). Normally this bit is the complement of the DSR
input. In Loopback mode this bit is equivalent to the DTR bit in the MCR
register.
CTS (active HIGH, logic 1). CTS functions as hardware flow control signal
input if it is enabled via MCR[5]. Flow control (when enabled) allows starting
and stopping the transmissions based on the external modem CTS signal. A
logic 1 at the CTS pin will stop SC16C554B/554DB transmissions as soon as
current character has finished transmission. Normally MSR[4] is the
complement of the CTS input. However, in the Loopback mode, this bit is
equivalent to the RTS bit in the MCR register.
ΔCD
ΔRI
ΔDSR
ΔCTS
Logic 0 = No CD change (normal default condition).
Logic 1 = The CD input to the SC16C554B/554DB has changed state
since the last time it was read. A modem Status Interrupt will be generated.
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C554B/554DB has changed from a
logic 0 to a logic 1. A modem Status Interrupt will be generated.
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C554B/554DB has changed state
since the last time it was read. A modem Status Interrupt will be generated.
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C554B/554DB has changed state
since the last time it was read. A modem Status Interrupt will be generated.
[1]
Rev. 4 — 8 June 2010
[1]
[1]
[1]
SC16C554B/554DB
© NXP B.V. 2010. All rights reserved.
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