SCC68692E1A44,512 NXP Semiconductors, SCC68692E1A44,512 Datasheet - Page 12

• Manufacturer Part Number: SCC68692E1A44,512
• Description: IC DUART 44PLCC
• Manufacturer: NXP Semiconductors

Specifications of SCC68692E1A44,512

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 3Bit
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935027030512; SCC68692E1A44; SCC68692E1A44

is programmed by MR1A[4:3], and the polarity of the forced parity bit
Philips Semiconductors
MR1A[4:3| – Channel A Parity Mode Select
If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
MR1A[2] – Channel A Parity Type Select
This bit selects the parity type (odd or even) if the ‘with parity’ mode
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multidrop mode it selects
the polarity of the A/D bit.
MR1A[1:0] – Channel A Bits Per Character Select
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
MR2A – Channel A Mode Register 2
MR2A is accessed when the Channel A MR pointer points to MR2,
which occurs after any access to MR1A. Accesses to MR2A do not
change the pointer.
MR2A[7:6] – Channel A Mode Select
Each channel of the DUART can operate in one of four modes.
MR2A[7:6] = 00 is the normal mode, with the transmitter and
receiver operating independently. MR2A[7:6] = 01 places the
channel in the automatic echo mode, which automatically
re-transmits the received data. The following conditions are true
while in automatic echo mode:
1. Received data is re-clocked and retransmitted on the TxDA out-
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the transmitter need not be
4. The Channel A TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not regenerated for trans-
6. Character framing is checked, but the stop bits are retransmitted
7. A received break is echoed as received until the next valid start
8. CPU to receiver communication continues normally, but the CPU
Two diagnostic modes can also be configured. MR2A[7:6] = 10
selects local loopback mode. In this mode:
1. The transmitter output is internally connected to the receiver
2. The transmit clock is used for the receiver.
3. The TxDA output is held HIGH.
4. The RxDA input is ignored.
5. The transmitter must be enabled, but the receiver need not be
6. CPU to transmitter and receiver communications continue nor-
The second diagnostic mode is the remote loopback mode, selected
by MR2A[7:6] = 11. In this mode:
1. Received data is re-clocked and retransmitted on the TxDA out-
2. The receive clock is used for the transmitter.
2004 Mar 03
Dual asynchronous receiver/transmitter (DUART)
put.
enabled.
mission, i.e. transmitted parity bit is as received.
as received.
bit is detected.
to transmitter link is disabled.
input.
enabled.
mally.
put.
12
the underrun condition, the issuing of the transmitter disable must be
3. Received data is not sent to the local CPU, and the error status
4. The received parity is not checked and is not regenerated for
5. The receiver must be enabled.
6. Character framing is not checked, and the stop bits are retrans-
7. A received break is echoed as received until the next valid start
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes: if the
de-selection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop has been retransmitted.
MR2A[5] – Channel A Transmitter Request-to-Send Control
CAUTION: When the transmitter controls the OP pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather, it signals that the transmitter has finished the transmission
(i.e., end of block).
This bit allows deactivation of the RTSN output by the transmitter.
This output is manually asserted and negated by the appropriate
commands issued via the command register. MR2[5] set to ‘1’
caused the RTSN to be reset automatically one bit time after the
character(s) in the transmit shift register and in the THR (if any) are
completely transmitted (including the programmed number of stop
bits) if a previously issued transmitter disable is pending. This
feature can be used to automatically terminate the transmission as
follows:
1. Program the auto-reset mode: MR2[5] = 1
2. Enable transmitter, if not already enabled
3. Assert RTSN via command
4. Send message
5. After the last character of the message is loaded to the THR,
6. The last character will be transmitted and the RTSN will be reset
NOTE: The transmitter is in an underrun condition when both the
TxRDY and the TxEMT bits are set. This condition also exists
immediately after the transmitter is enabled from the disabled or
reset state. When using the above procedure with the transmitter in
delayed from the loading of a single, or last, character until the
TxRDY becomes active again after the character is loaded.
MR2A[4] – Channel A Clear-to-Send Control
If this bit is ‘0’, CTSAN has no effect on the transmitter. If this bit is a
‘1’, the transmitter checks the state of CTSAN (IPO) each time it is
ready to send a character. If IPO is asserted (LOW), the character is
transmitted. If it is negated (HIGH), the TxDA output remains in the
marking state and the transmission is delayed until CTSAN goes
LOW. Changes in CTSAN while a character is being transmitted do
not affect the transmission of that character.
conditions are inactive.
transmission, i.e., transmitted parity is as received.
mitted as received.
bit is detected.
disable the transmitter. (If the transmitter is underrun, a special
case exists. See note below.)
one bit time after the last stop bit is sent.
SCC68692
Product data